{"id":1067,"date":"2021-12-23T06:25:42","date_gmt":"2021-12-23T06:25:42","guid":{"rendered":"https:\/\/ascendas-asia.com\/?post_type=our_courses&#038;p=1067"},"modified":"2024-06-11T16:39:56","modified_gmt":"2024-06-11T08:39:56","slug":"designing-with-the-versal-acap-pci-express-systems","status":"publish","type":"our_courses","link":"https:\/\/ascendas-asia.com\/vi\/our_courses\/designing-with-the-versal-acap-pci-express-systems\/","title":{"rendered":"Designing with the Versal Adaptive Soc: PCI Express Systems"},"content":{"rendered":"<p>This two-day course introduces the features and capabilities of the PCIe\u00ae and Cache Coherent Interconnect blocks in the Versal\u2122 architecture. Learn how to implement a Versal ACAP PCI Express\u00ae solution in custom applications to improve time to market.<\/p>\n<p>The emphasis of this course is on:<\/p>\n<ul class=\"ul-listing\">\n<li>Describing the Xilinx PCI Express design methodology<\/li>\n<li>Enumerating various Xilinx PCI Express core products<\/li>\n<li>Selecting the PCI Express IP cores from the Vivado\u00ae Design Suite<\/li>\n<li>Generating PCI Express example designs and simple applications<\/li>\n<li>Identifying the advanced capabilities of the PCIe specification<\/li>\n<\/ul>\n<p>This course also focuses on the AXI-Streaming interconnect.<\/p>","protected":false},"excerpt":{"rendered":"<p>This two-day course introduces the features and capabilities of the PCIe\u00ae and Cache Coherent Interconnect blocks in the Versal\u2122 architecture. Learn how to implement a Versal ACAP PCI Express\u00ae solution in custom applications to improve time to market. The emphasis of this course is on: Describing the Xilinx PCI Express design methodology Enumerating various Xilinx [&hellip;]<\/p>","protected":false},"author":1,"featured_media":7543,"parent":0,"menu_order":49,"template":"","format":"standard","meta":{"content-type":"","_links_to":"","_links_to_target":""},"courses_category":[21,26],"class_list":["post-1067","our_courses","type-our_courses","status-publish","format-standard","has-post-thumbnail","hentry","courses_category-xilinx-fpga-training-course","courses_category-versal"],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v22.1 (Yoast SEO v27.7) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Designing with the Versal Adaptive Soc: PCI Express Systems - TechSource Systems &amp; Ascendas Systems Group<\/title>\n<meta name=\"description\" content=\"This training course introduces the features and capabilities of the PCIe\u00ae and Cache Coherent Interconnect blocks in the Versal\u2122 architecture\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/ascendas-asia.com\/vi\/our_courses\/designing-with-the-versal-acap-pci-express-systems\/\" \/>\n<meta property=\"og:locale\" content=\"vi_VN\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Designing with the Versal Adaptive Soc: PCI Express Systems\" \/>\n<meta property=\"og:description\" content=\"This training course introduces the features and capabilities of the PCIe\u00ae and Cache Coherent Interconnect blocks in the Versal\u2122 architecture\" \/>\n<meta property=\"og:url\" content=\"https:\/\/ascendas-asia.com\/vi\/our_courses\/designing-with-the-versal-acap-pci-express-systems\/\" \/>\n<meta property=\"og:site_name\" content=\"TechSource Systems &amp; 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