{"id":1077,"date":"2021-12-23T06:35:18","date_gmt":"2021-12-23T06:35:18","guid":{"rendered":"https:\/\/ascendas-asia.com\/?post_type=our_courses&#038;p=1077"},"modified":"2024-06-12T14:00:59","modified_gmt":"2024-06-12T06:00:59","slug":"designing-with-the-ultrascale-and-ultrascale-architectures","status":"publish","type":"our_courses","link":"https:\/\/ascendas-asia.com\/th\/our_courses\/designing-with-the-ultrascale-and-ultrascale-architectures\/","title":{"rendered":"Designing with the Ultrascale and Ultrascale+ Architectures"},"content":{"rendered":"<p>This course introduces the UltraScale\u2122 and UltraScale+\u2122<br \/>\narchitectures to both new and experienced designers.<\/p>\n<p>The emphasis is on:<\/p>\n<ul class=\"ul-listing\">\n<li>Introducing CLB resources, clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources, and source-synchronous resources<\/li>\n<li>Describing improvements to the dedicated transceivers and<br \/>\nTransceiver Wizard<\/li>\n<li>Reviewing the Memory Interface Generator (MIG) and DDR4 memory interface capabilities<\/li>\n<li>Migrating existing designs and IP to the UltraScale architecture<br \/>\nwith optimal use of the Vivado\u00ae Design Suite<\/li>\n<\/ul>\n<p>What&#8217;s New for 2021.2<\/p>\n<ul class=\"ul-listing\">\n<li>All labs have been updated to the latest software versions<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"<p>This course introduces the UltraScale\u2122 and UltraScale+\u2122 architectures to both new and experienced designers. The emphasis is on: Introducing CLB resources, clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources, and source-synchronous resources Describing improvements to the dedicated transceivers and Transceiver Wizard Reviewing the Memory Interface Generator (MIG) and [&hellip;]<\/p>","protected":false},"author":1,"featured_media":7548,"parent":0,"menu_order":56,"template":"","format":"standard","meta":{"content-type":"","_links_to":"","_links_to_target":""},"courses_category":[21,27],"class_list":["post-1077","our_courses","type-our_courses","status-publish","format-standard","has-post-thumbnail","hentry","courses_category-xilinx-fpga-training-course","courses_category-vivado-fpga-design"],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v22.1 (Yoast SEO v27.7) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Designing with the Ultrascale and Ultrascale+ Architectures - TechSource Systems &amp; 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