{"id":1065,"date":"2021-12-23T06:23:01","date_gmt":"2021-12-23T06:23:01","guid":{"rendered":"https:\/\/ascendas-asia.com\/?post_type=our_courses&#038;p=1065"},"modified":"2024-07-31T13:33:19","modified_gmt":"2024-07-31T05:33:19","slug":"high-level-synthesis-with-the-vitis-uniified-ide","status":"publish","type":"our_courses","link":"https:\/\/ascendas-asia.com\/th\/our_courses\/high-level-synthesis-with-the-vitis-uniified-ide\/","title":{"rendered":"High-Level Synthesis with the Vitis Unified IDE"},"content":{"rendered":"<p>This two-day course provides a thorough introduction to the Vitis\u2122 High-Level Synthesis (HLS) using the AMD Vitis\u2122 Unified IDE.<br \/>\nThe focus of this course is on:<\/p>\n<div class=\"row\">\n<ul class=\"ul-listing\">\n<li>Converting C\/C++ designs into RTL implementations<\/li>\n<li>Learning the HLS component development flow<\/li>\n<li>Creating I\/O interfaces for designs<\/li>\n<li>Applying different optimization techniques to design<\/li>\n<li>Improving throughput, area, latency, and logic by using different HLS pragmas\/directives<\/li>\n<li>Exporting IP that can be used with the Vivado\u00ae IP catalog<\/li>\n<li>Migrating designs from the classic Vitis HLS tool to the Vitis Unified IDE<\/li>\n<\/ul>\n<p>What&#8217;s New for 2023.2<\/p>\n<ul class=\"ul-listing\">\n<li style=\"list-style-type: none\">\n<ul class=\"ul-listing\">\n<li>Restructured existing Vitis HLS content to align with the HLS component development flow<\/li>\n<li>Revamped all labs for compatibility with the Vitis Unified IDE<\/li>\n<li>Integrated coverage of the v++ and vitis-run command options<\/li>\n<li>Added information on Vitis HLS Code Analyzer and the Dataflow Viewer<\/li>\n<li>Added a module dedicated to optimizing AXI system performance<\/li>\n<li>Added a module covering Vitis HLS Libraries<\/li>\n<li>Added a module and lab for migrating from the classic Vitis HLS tool to the Vitis Unified IDE<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/div>","protected":false},"excerpt":{"rendered":"<p>This two-day course provides a thorough introduction to the Vitis\u2122 High-Level Synthesis (HLS) using the AMD Vitis\u2122 Unified IDE. The focus of this course is on: Converting C\/C++ designs into RTL implementations Learning the HLS component development flow Creating I\/O interfaces for designs Applying different optimization techniques to design Improving throughput, area, latency, and logic [&hellip;]<\/p>","protected":false},"author":1,"featured_media":7558,"parent":0,"menu_order":48,"template":"","format":"standard","meta":{"content-type":"","_links_to":"","_links_to_target":""},"courses_category":[90,21,28,94],"class_list":["post-1065","our_courses","type-our_courses","status-publish","format-standard","has-post-thumbnail","hentry","courses_category-vitis-unified-software-platform","courses_category-xilinx-fpga-training-course","courses_category-language","courses_category-high-level-synthesis-vitis"],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v22.1 (Yoast SEO v27.7) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>High-Level Synthesis with the Vitis Unified IDE - TechSource Systems &amp; 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