VHDL Design Expert

Comprehensive course that covers the application of VHDL for programmable logic and ASIC design.

Course
Highlights

Based on Xilinx industry standard, this total training package can be considered as the minimum training requirement for project readiness.

The course is based on a 5-day agenda. Comprising 2 modules, it can be taken in two stages by attending the individual modules or the full 5-day training package with an interval of at least 2 months.

Module 1:Designing with VHDL (3-day) is a thorough introduction to the VHDL language. The emphasis is on writing solid synthesizable code and enough simulation code to write a viable testbench. Structural, Register Transfer Level (RTL), and behavioral coding styles are covered. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn best coding practices that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course.

Module 2:Advanced VHDL (2-day) is specially designed to increase your VHDL proficiency by learning advanced techniques that will help you write more robust and reusable code. This is targeted toward designers who already have some experience with VHDL. The course highlights modeling, testbenches, RTL/synthesizable design, and techniques aimed at creating parameterizable and reusable designs. The majority of class time is spent in challenging hands-on labs as compared to lecture modules.

Who Should
Attend

Engineers who want to use VHDL effectively for modeling, design, and synthesis of digital designs.

Course
Prerequisites

Basic digital design knowledge.

Course
Benefits

After completing this comprehensive training, you will have the necessary skills to do the following.

Designing with VHDL

Implement the VHDL portion of coding for synthesis
Identify the differences between behavioral and structural coding styles
Distinguish coding for synthesis versus coding for simulation
Use scalar and composite data types to represent information
Use concurrent and sequential control structure to regulate
information flow
Implement common VHDL constructs (finite state machines
[FSMs], RAM/ROM data structures)
Simulate a basic VHDL design
Write a VHDL testbench and identify simulation-only constructs
Identify and implement coding best practices
Optimize VHDL code to target specific silicon resources within the Xilinx FPGA
Create and manage designs within the Vivado Design Suite
environment

Advanced VHDL

Write efficient and reusable RTL, testbenches, and packages
Create self-testing testbenches
Create realistic models
Use the text I/O capabilities of the VHDL language
Store simulation data dynamically
Create parameterized code for design reuse

Partners

TechSource Systems is MathWorks Authorised Reseller and Training Partner

Upcoming Program

Please keep me posted on the next schedule
Please contact me to arrange customized/ in-house training

Course Outline

Module 1: Designing with VHDL

Introduction to VHDL

Objective: Discusses the history of the VHDL language and provides an overview of the different features of VHDL.

Describe the original intent of VHDL and how this intent has influenced the design of the language
Define key terms and concepts in relationship to VHDL
Describe the different coding styles that are available in VHDL

VHDL Design Units

Objective: Provides an overview of typical VHDL code, covering design units such as libraries, packages, entities, architectures, and configuration.

Describe the design units that are available in VHDL code
Define the library and packages and how they are declared
Explain entity and architecture syntax and declarations

VHDL Objects, Keywords, Identifiers

Objective: VHDL Objects, Keywords, Identifiers.

Use appropriate keywords in VHDL
Describe identifiers and the rules for writing identifiers
Comment a piece of VHDL code

Scalar Data Types

Objective: Covers both intrinsic and commonly used data types.

Use appropriate data types when declaring ports and signals

List legal values for std_logic data types
Create scalar data types

Composite Data Types

Objective: Covers composite data types (arrays and records).

Describe what composite data types are
Create composite data types (array and record)

Declare one-dimensional and two-dimensional arrays

VHDL Operators

Objective: Reviews all VHDL operator types.

Analyze all the operators that are available in VHDL

Use these operators in VHDL code

Concurrency in VHDL

Objective: Describes concurrent statements and how signals help in achieving concurrency.

Describe what a signal is and how it behaves in a concurrent use
Describe how to define a constant and how it behaves

Define the event and transaction
Define the concept of data cycles

Concurrent Assignments

Objective: Covers both conditional and unconditional assignments.

Define the types of concurrent statements
Use the generate statement in your code

Show how to make unconditional and conditional assignments

Processes and Variables

Objective: Introduces sequential programming techniques for a concurrent language. Variables are also discussed.
Objective: Covers both conditional and unconditional assignments.

Describe what a process is and why it is beneficial
Explain the purpose and proper implementation of a process sensitivity list
Show how to define variables and compare and contrast them to signals

Conditional Statements in VHDL: if/else, case

Objective: Describes conditional statements such as if/else and case statements.

Enumerate control structures within a process

Use if/else and case statements in your code

Sequential Looping Statements

Objective: Introduces the concept of looping in both the simulation and synthesis environments.

Describe the available looping structures in VHDL and where they can be used

Delays in VHDL: wait Statement

Objective: Describes conditional statements such as if/else and case statements.

Describe the delay types available in VHDL
Define the four types of the wait statement

List the key concepts for good coding style with respect to synchronous processes

Introduction to the VHDL Testbench

Objective: Introduces the concept of the VHDL testbench to verify the functionality of a design.

Define a testbench
Write a simple testbench

Identify the basic components of a testbench

VHDL Assert Statements

Objective: Describes the concept of VHDL assertions.

Define a VHDL assertion and its syntax

Write an assert statement

VHDL Attributes

Objective: Describes attributes, both predefined and user defined.

Enumerate the three classes of “tic” attributes
Use signal attributes in VHDL code

Demonstrate how to locate and employ synthesis and implementation attributes

VHDL Subprograms

Objective: Covers the use of subprograms in verification and RTL code to model functional blocks.

Describe the use of subprograms in VHDL coding

Differentiate between functions and procedures

VHDL Functions

Objective: Describes functions, which are integral to reusable and
maintainable code.

Write functions in your VHDL code

Use function overloading in the code

VHDL Procedures

Objective: Describes procedures, common constructs that are also important for reusing and maintaining code.

Describe procedures and their syntax

Write procedures in your VHDL code

VHDL Libraries and Packages

Objective: Demonstrates how libraries and packages are declared and used.

Enumerate the frequently used standard libraries and identify the relevant contents of each

Explain how to create packages and libraries
Describe the contents of a package and a library

Interacting with Simulation

Objective: Describes how to interact with a simulation via text I/O.

Indicate the various points in the development flow appropriate for simulation

Explain the contents of the TextIO library (output capabilities only)

Finite State Machine Overview

Objective: Provides an overview of finite state machines, one of the more commonly used circuits.

Describe what a finite state machine is

Describe the basic VHDL considerations for a finite state machine

Mealy Finite State Machine

Objective: Describes how to implement a Mealy state machine in which the output is dependent on both the current state and the inputs.

Describe what a Mealy finite state machine is

Moore Finite State Machine

Objective: Demonstrates how to implement a Moore state machine in which the output is dependent on the current state only.

Describe what a Moore finite state machine is

FSM Coding Guidelines

Objective: Describes the guidelines and recommendations for using one or more procedural blocks when coding a finite state machine.

Enumerate principle good programming practices when using state machines

List several mechanisms for implementing finite state machines

Vivado Simulator and Race Conditions in VHDL

Objective: Introduces the Vivado simulator simulation environment. Race conditions are also discussed.

Describe how the Vivado® simulator works

Using the Vivado simulator
Define race conditions in VHDL

Writing a Good Testbench

Objective: Explores how time-agnostic, self-checking testbenches can be written and applied.

Describe how a self-checking testbench can be constructed

Illustrate proper annotation techniques

Targeting Xilinx FPGAs

Objective: Focuses on Xilinx-specific implementation and chip-level optimization.

Describe the challenges of using an HDL approach for FPGA designs
Identify the factors that directly affect FPGA timing and performance
Identify the trade-offs and guidelines for logic inference and instantiation

Describe typical synthesis compiler options and their benefits
List synthesis considerations unique to Xilinx FPGAs

Module 2: Advanced VHDL

VHDL Overview

efficient and reusable RTL, testbenches, and packages
self-testing testbenches
realistic models

text I/O capabilities of the VHDL language
Storing simulation data dynamically
parameterized code for design reuse

Simulation Concepts

differences between analysis, elaboration, and execution
appropriate time to use transport and inertial delay

how concurrency is modeled
Vivado® simulator for the various simulation points

Advanced Data Types

Natural
Unconstrained
Aliases
Shared variables
Protected types

User-defined types: records, arrays, types, subtypes
Physical types
Access
File

Subprograms and Design Attributes

impure functions
how to use procedure-class parameters

design attributes
advantages of using subprograms

Access Type Techniques and Blocks

commonly used techniques using access types
how blocks can be used to associate logic

File I/O

VHDL Text IO package for reading and writing to text files

Advanced Techniques in VHDL

existing IEEE packages and third-party packages
Implement controlled jitter and spectrum spreading

real-world timing problems, including Trace-length mismatches and Asynchronous stimulus

Supporting Multiple Platforms

mechanisms for supporting alternate architectures
proper syntax of conditional generate and configuration statements and their proper use

alternate methods for supporting multiple platforms (directory structures and scripts
set up a multiple-architecture design in the Vivado® Design Suite

Non-Integer Numbers

contents and relevance of the IEEE-proposed standard for synthesis of floating point numbers

alternatives to floating point numbers
theory behind floating point representation

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VHDL Design Expert