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Verilog & FPGA Design Expert
Comprehensive training which provides minimum requirement for FPGA related project readiness.
Course
Highlights
‘Verilog & FPGA Design’ is a comprehensive training package that comprises of 2 course modules: Designing with Verilog and Designing FPGAs Using the Vivado Design Suite 1. Based on Xilinx industry standard, this 6-day training package can be considered as the minimum training requirement for project readiness.
Designing with Verilog (3-day) is a comprehensive course which provides a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001. You will gain valuable hands-on experience. Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.
Designing FPGAs Using the Vivado Design Suite 1 (2-day) offers introductory training on the Vivado® Design Suite and demonstrates the FPGA design flow for those uninitiated to FPGA design.
The course provides experience with creating a Vivado Design Suite project with source files, simulating a design, performing pin assignments, applying basic timing constraints, synthesizing and implementing, debugging a design, generating and downloading a bitstream onto a demo board.
Hands-on Project (1-day) on the last day allows you to test your knowledge and apply your skills immediately. No documentation, no labs instructions, you will face the real challenge to do a full FPGA design flow project with the guidance of our instructor.
Who Should
Attend
Digital designers who are interested in FPGA design training and want to use Verilog effectively for modeling, design, and synthesis of digital designs and learn to use Xilinx FPGAs.
Course
Prerequisites
Basic digital design knowledge.
Course
Benefits
After completing this comprehensive training, you will have the
necessary skills to do the following:
Designing with Verilog
- Write RTL Verilog code for synthesis
- Write Verilog test fixtures for simulation
- Create a finite state machine (FSM) by using Verilog
- Target and optimize Xilinx FPGAs by using Verilog
- Use enhanced Verilog file I/O capabilities
- Run a timing simulation by using Xilinx Simprim libraries
- Create and manage designs within the Vivado Design Suite environment
- Download to the evaluation demo board
FPGA Design Expert
- Use the New Project Wizard to create a new Vivado IDE project
- Describe the supported design flows of the Vivado IDE
- Generate a DRC report to detect and fix design issues early in the flow
- Use the Vivado IDE I/O Planning layout to perform pin assignments
- Synthesize and implement the HDL design
- Apply clock and I/O timing constraints and perform timing analysis
- Describe the “baselining” process to gain timing closure on a
design - Use the Schematic and Hierarchy viewers to analyze and
cross-probe a design - Use the Vivado logic analyzer and debug cores to debug a design
Partners
Upcoming Program
- Please keep me posted on the next schedule
- Please contact me to arrange customized/ in-house training
Course Outline
Introduction to Verilog
Objective: Discusses the history of the Verilog language and provides an overview of the different features of Verilog.
- origin of the Verilog HDL
- common “levels of abstraction” for hardware modeling
- subsets of the Verilog syntax
- basic guidelines for creating a hierarchical design structure
- accesses components from the vendor-specific library and why instantiation may be preferable to inference
Verilog Keywords and Identifiers
Objective: Discusses the data objects that are available in the Verilog language as well as keywords and identifiers.
- keywords and identifiers found in the Verilog environment
Verilog Data Values and Number Representation
Objective: Covers what data values are in Verilog, as well as how to represent numbers in Verilog.
- data values supported by Verilog
- how numbers are represented in the Verilog environment
Verilog Data Types
Objective: Covers the various data types in Verilog.
- objects in the Verilog environment
- correct Verilog data type throughout your source code
Verilog Buses and Arrays
Objective: Covers buses and arrays in Verilog.
- what is data bus
- Declare, assign to, and manipulate portions of a data bus
- memory structure using arrays
Verilog Modules and Ports
Objective: Describes both the syntax and hierarchy for a Verilog module, port declarations, and the difference between reg versus wire.
- basic Verilog module description
- module ports based on their intended usage
- hierarchical structures in Verilog code
Verilog Operators
Objective: Shows the syntax for all Verilog operators.
- types and classes of Verilog operators
- common Verilog operators to model a variety of functions
- arithmetic operators to perform standard arithmetic functions on signals and buses
Continuous Assignment
Objective: Introduces the Verilog continuous assignment statement.
- Model logic by using a Verilog assign statement
- delay specifications on the logic
Gate-Level Modeling
Objective: Introduces gate-level modeling in Verilog.
- design ingate-level modeling
- gate delays to the logic primitives
Procedural Assignment
Objective: Provides an introduction to procedural assignments in Verilog, including their usage and restrictions.
- design using behavioral modeling
- use of Verilog initial and always procedure blocks
Blocking and Non-Blocking Procedural Assignment
Objective: Introduces blocking and non-blocking assignment statements in Verilog.
- blocking and non-blocking assignments
- Use blocking and non-blocking statements appropriately in design
Procedural Timing Control
Objective: Introduces the timing control methods that are used in procedural assignments.
- time control in procedural blocks
- different types of procedural timing control
Verilog Conditional Statements: if_else
Objective: Describes the if/else conditional statement.
- if-else statements to produce optimal logic
- important guidelines for effective default statements
Verilog Conditional Statements: case
Objective: Describes the case conditional statement.
- case statements to produce optimal logic
- important guide lines while writing a case statement
Verilog Loop Statements
Objective: Introduces the different types of Verilog loop statements.
- loop statements to control repeated execution of statements
- different loop statements available in Verilog
Introduction to the Verilog Testbench
Objective: Introduces the concept of the Verilog testbench.
- concept and general application of a testbench
- simulation only and synthesizable constructs
- basic recommendations for effective design verification
- necessary components for creating and executing a Verilog testbench
- basic input stimulus and model input clocks
System Tasks
Objective: Provides a basic understanding of system tasks.
- $display, $strobe, and $monitor for simulator tasks
- Display simulation time in the desired format
Verilog Subprograms
Objective: Covers the use of subprograms in verification and RTL code to model functional blocks.
- use of subprograms in Verilog HDL coding
- functions and tasks
Verilog Functions
Objective: Describes functions, which are integral to reusable and maintainable code.
- Declare and use functions within Verilog code
- types offunctions
Verilog Tasks
Objective: Covers tasks in Verilog.
- Declare and use tasks within Verilog code
Verilog Compiler Directives
Objective: Describes Verilog compiler directives.
- compiler directives in Verilog HDL coding
Verilog Parameters
Objective: Covers Verilog parameters and the local parameter concept.
- what is a parameter
- Declare the local parameter as appropriate
- Update the value of a parameter
Verilog Generate Statements
Objective: Introduces the Verilog generate statement.
- Verilog generate statement for repetitive or conditional logic implementation
- different methods to create generate statements in your design
Timing Checks
Objective: Covers the timing check statements in Verilog and talks about the specify block.
- timing checks statements in design
- the specify block
- timing violations for design
Finite State Machines
Objective: Provides an overview of finite state machines, one of the more commonly used circuits.
- what is a finite state machine
- basic Verilog considerations for FSM
Mealy Finite State Machine
Objective: Describes the Mealy FSM and how to code for it.
- what is a Mealy finite state machine
Moore Finite State Machine
Objective: Describes the Moore FSM and how to code for it.
- what is a Moore finite state machine
FSM Coding Guidelines
Objective: Shows how to model an FSM of any complexity in Verilog and describes recommendations for performance and reliability.
- implications of using one or more procedural blocks while coding for FSM
- guidelines and recommendation presented in this module
Avoiding Race Conditions in Verilog
Objective: Objective: Describe what a race condition is and provides steps to avoid this condition.
- what is a race condition
- types of race conditions
- simulation event queue
- guidelines to avoid race conditions
File I/O: Introduction
Objective: Covers using basic and enhanced Verilog file I/O capabilities for more robust design verification.
- benefits of using Verilog file I/O during simulation
- process for creating and opening files and controlling access
- Verilog $readmemb or $readmemh during simulation
File I/O: Read Functions
Objective: Objective: Covers Verilog file I/O read capabilities.
- enhanced Verilog file I/O read operations
- $fgets and $fscanf functions during simulation
File I/O: Write Functions
Objective: Covers Verilog file I/O write capabilities.
- enhanced Verilog file I/O write operations
- when to use $fwrite and $fdisplay during simulation
Targeting Xilinx FPGAs
Objective: Focuses on Xilinx-specific implementation and chip-level optimization.
- challenges of using an HDL approach for FPGA designs
- factors that directly affect FPGA timing and performance
- trade-offs and guidelines for logic inference and instantiation
- typical synthesis compiler options and their benefits
- synthesis considerations unique to Xilinx FPGAs
Introduction to FPGA Architecture, 3D ICs, SoCs, ACAPs
Objective: Overview of FPGA architecture, SSI technology, and SoC device architecture.
- FPGA architecture
- major building blocks of FPGAs
- stacked silicon-based 3D IC devices
- SoC devices
- Describe Adaptive Compute Acceleration Platforms (ACAPs)
UltraFast Design Methodology: Board and Device Planning
Objective: Introduces the methodology guidelines covered in this course and the UltraFast Design Methodology checklist.
- UltraFastTM Design Methodology checklist to identify common mistakes and decision points throughout the design process
- which FPGA device resources need particular attention in a design
- importance of following a proper pin planning methodology
- what power considerations you need to take into account when planning for the PCB design
- Fix design issues earlier in the design flow
HDL Coding Techniques
Objective: Covers basic digital coding guidelines used in an FPGA design.
- use of control signals (sets, resets, and clock enables) can impact your device utilization
- Describe the benefits of following Xilinx recommendations on resets
- difference between inference and instantiation
- design coding to infer the dedicated hardware resources
- Describe the recommended coding techniques
Introduction to Vivado Design Flows
Objective: Introduces the Vivado design flows: the project flow and non-project batch flow.
- various design flows in the Vivado® Design Suite
- RTL-to-bitstream design flow
- supported use models in the Vivado Design Suite
- system-level integration flows
Vivado Design Suite Project-based Flow
Objective: Introduces the project-based flow in the Vivado Design Suite: creating a project, adding files to the project, exploring the Vivado IDE, and simulating the design.
- project mode use model in the Vivado® Design Suite
- structure and files of a project
- Vivado Design Suite project in project mode
Introduction to Vivado Reports
Objective: Generate and use Vivado timing reports to analyze failed timing paths.
- different reports generated by the Vivado® IDE
- timing reports and commands used by the Vivado IDE
Behavioral Simulation
Objective: Describes the process of behavioral simulation and the simulation options available in the Vivado® IDE.
- benefits of behavioral simulation
- behavioral simulation on a design
- functionality of a design
Xilinx Power Estimator Spreadsheet
Objective: Estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE.
- estimate power consumption by using the Xilinx Power Estimator (XPE) spreadsheet
Vivado Synthesis and Implementation
Objective: Create timing constraints according to the design scenario and synthesize and implement the design. Optionally, generate and download the bitstream to the demo board.
- synthesis and implementation options and directives
- Synthesize and implement an HDL design
- programs that are available as part of the synthesis and implementation process
Vivado IP Flow
Objective: Customize IP, instantiate IP, and verify the hierarchy of your design IP.
- managed IP flow in the Vivado® IDE
- IP catalog from the project to customize and add IP to the design
- usage of IP output files
- synthesis options for IP
- block design container feature in the Vivado IP integrator
Vivado Design Suite I/O Pin Planning
Objective: Use the I/O Pin Planning layout to perform pin assignments in a design.
- I/O planning project in the Vivado® IDE
- Package Pins and I/O Ports windows in the Vivado IDE
- I/O ports interactivity
- relationship between I/O banks and the logic in your design
Introduction to Clock Constraints
Objective: Apply clock constraints and perform timing analysis.
- what is a clock
- appropriate clock constraints for your design
- input jitter and clock latency
- clocks present in the design
Generated Clocks
Objective: Use the report clock networks report to determine if there are any generated clocks in a design.
- generated clocks
- automatically and manually generated clocks
- relationship between a generated clock and the source clock
I/O Constraints and Virtual Clocks
Objective: Apply I/O constraints and perform timing analysis.
- appropriate input and output delays for your design
- virtual clocks for input and output delays in your design
- timing reports that involve inputs and outputs
Timing Constraints Wizard
Objective: Use the Timing Constraints Wizard to apply missing timing constraints in a design.
- Timing Constraints Wizard to create timing constraints
- completion of timing constraints using the Timing Constraints Wizard
Basics of Clock Gating and Static Timing Analysis
Objective: Describes the basics of clock gating and static timing analysis.
- basics of clock gating
- basics of static timing analysis
- setup and hold slack
Calculating Setup and Hold Timing
Objective: Reviews setup and hold timing calculations.
- setup and hold slacks
- input setup and hold analysis
- output setup and hold analysis
Introduction to FPGA Configuration
Objective: Describes how FPGAs can be configured.
- basic FPGA configuration process
- purpose of each of the FPGA configuration pins
- FPGA configuration files
Introduction to the Vivado Logic Analyzer
Objective: Overview of the Vivado logic analyzer for debugging a design.
- what is Vivado® Logic Analyzer (VLA), as well as the fundamental components that comprise the Vivado debug tool
- benefits of the Vivado logic analyzer
- basic probing flows to debug your design
Introduction to Triggering
Objective: Introduces the trigger capabilities of the Vivado logic analyzer.
- trigger mechanism of the Vivado® logic analyzer
- using the Run Trigger option
- captured data using the waveform view
Debug Cores
Objective: Understand how the debug hub core is used to connect debug cores in a design.
- ILA core and its properties
- VIO and IBERT core usage
- what the debug core hub is and why it is used
- debug core hub insertion and customization
Introduction to the Tcl Environment
Objective: Introduces Tcl (tool command language).
- popular uses and benefits of using Tcl commands in an FPGA design development flow
- how Tcl scripts can be executed from within the interactive environment
- ways of running the Vivado® IDE with Tcl commands
- access the help feature
Tcl Syntax and Structure
Objective: Understand the Tcl syntax and structure.
- basic syntax and language structure of Tcl
- Running Tcl commands and scripts interactively and in a shell
- Tcl command structure
- substitutions made by the Tcl parser
- comments and use the puts command
- strings, brackets, and quoting
Using Tcl Commands in the Vivado Design Suite Project Flow
Objective: Explains what Tcl commands are executed in a Vivado Design Suite project flow.
- contents of a basic Vivado® IDE script
- basic Tcl commands in a project-based flow
- Tcl script
Hands-on Project
FPGA Design Flow Hands-on practices.
