Customise Your Training
TechSource Systems is MathWorks Authorised Reseller and Training Partner
Signal Integrity and Board Design for Xilinx FPGAs
Connectivity Design
Signal Integrity and Board Design for Xilinx FPGAs
Learn when and how to apply signal integrity techniques to high-speed interfaces between Xilinx FPGAs and other components.
Course
Highlights
This three-day comprehensive course combines design techniques and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter.
You will work with IBIS models and complete simulations using Mentor Graphics HyperLynx. Other topics include managing PCB effects and on-chip termination. This course balances lecture modules with instructor demonstrations and practical hands-on labs.
Who Should
Attend
Digital designers, board layout designers, or scientists, engineers, and technologists seeking to implement Xilinx solutions. Also end users of Xilinx products who want to understand how to implement high-speed interfaces without incurring the signal integrity problems related to timing, crosstalk, and overshoot or undershoot infractions.
Course
Prerequisites
- FPGA design experience preferred (Designing FPGAs Using the
Vivado Design Suite 1 course or equivalent) - Familiarity with high-speed PCB concepts
- Basic knowledge of digital and analog circuit design
- Vivado™ tool knowledge is helpful
Course
Benefits
After completing this comprehensive training, you will have the
necessary skills to:
- Describe signal integrity effects
- Predict and overcome signal integrity challenges
- Simulate signal integrity effects
- Verify and derive design rules for the board design
- Apply signal integrity techniques to high-speed interfaces
between Xilinx FPGAs and semiconductor circuits - Plan your board design under FPGA-specific restrictions
- Supply the FPGAs with power
- Handle thermal aspects
Partners
Upcoming Program
- Please keep me posted on the next schedule
- Please contact me to arrange customized/ in-house training
Course Outline
Part 1 - Signal Integrity
Signal Integrity Introduction
Objective: introduce the Signal Integrity part of the course. Describe transmission lines. Interpret an IBIS model and correct common errors. Work with a signal integrity tool. Apply appropriate transmission line termination. Simulate simple trace structures. Simulate more complex structures like serial I/O or memory interfaces. Evaluate a design for the potential of signal degradation from signal propagation, reflection, crosstalk, and power supply. Recognize and mitigate the effects of signal propagation, reflection, crosstalk, and power supply on signal integrity.
Transmission Lines
Objective: Describe the nature of a transmission line. Explain the significance of harmonic magnitude. Discuss the importance of rise and fall times. Identify general issues relating to signal integrity design.
- Critical Trace Length in Time Domain
- Critical Trace Length in Frequency Domain
- What is High Speed?
- Transmission Line
IBIS Models and SI Tools
Objective: Describe some modeling and simulation considerations before the discussion on reflection and crosstalk should begin. Describe the IBIS file. Explain the importance of an IBIS editor. Identify the components of an IBIS file. Describe main features of a signal integrity tool. Create simple structures for signal integrity simulation with the HyperLynx tool.
- IBIS Files
- IBIS Editor
- Xilinx IBIS Model
- SI Tools
- SI Tool Example: HyperLynx
- Lab 1: Invoking HyperLynx
Reflections
Objective: Discuss reflections on transmission lines. Explain the reflection effect and how to minimize reflection during termination. Describe the effect of reflection. Reduce the reflection by termination. Describe the reflection for different topologies. Simulate reflection effects.
- Reflection Effects
- Reflection Calculations
- Trace Termination
- Reflection on Different Topologies
- Lab 2: Reflection Analysis
Crosstalk
Objective: Describe crosstalk on transmission lines. Explain the crosstalk effect and how to minimize crosstalk by trace geometry or dielectric thickness.
- Crosstalk Basics
- Crosstalk Calculations
- Minimizing Crosstalk
- Lab 3: Crosstalk Analysis
Part 1 - Signal Integrity (Continue)
Signal Integrity Analysis
Objective: Describe the principle SI analysis methods. Expand your modeling for packages and vias. Describe system-wide SI analysis. Integrate design kits into your environment.
- Methods for SI Analysis
- Additional Components for Simulation
- System Analysis
Power Integrity Issues
Objective: Describe power supply impedance considerations. Describe power supply inductance considerations. Describe the bypassing capacitor function and realization. Handle SI issues for power supply at the board level.
- Impedance and Bypass Capacitors
- Bypass Capacitors
- Power Supply on Board Level
- Tool Support
Signal Integrity Summary
Objective: Provide a summary of the signal integrity part of the course.
- Rules for Estimating SI Effects
- Guidelines for SI Design
Part 2 - Board Design
Board Design Introduction
Objective: Determine the power supply requirements for a PCB. Realize an appropriate power supply on a PCB. Realize configuration solutions on a PCB. Describe the requirements and realizations for signal interfacing. Describe some PCB considerations. Evaluate FPGA thermal aspects for a PCB and design appropriate thermal management. Identify the tools to apply to particular board design issues.
FPGA Power Supply
Objective: Describe power supply impedance considerations. Describe power supply inductance considerations. Describe the bypassing capacitor function and realization. Handle SI issues for power supply at the board level.
- Power Supply Design Flow
- Power Supply Estimation
- Supply Voltage Generation
- Power Distribution and Bypassing
- Reference Voltages
- Serial Transceiver Power Supply
- XADC Power Supply
- Lab 4: Power Analysis
FPGA Configuration and PCB
Objective: Describe configuration issues that are important in the board design process. Describe the configuration interfaces and their PCB requirements. Describe the configuration memory and their PCB requirements. Identify some typical configuration applications.
- Configuration Ports
- Configuration Interfaces
- Configuration Memory
- Configuration Applications
- Board Design Issues
Part 2 - Board Design (Continue)
Signal Interfacing – Part A: Interfacing in General
Objective: Describe FPGA interface options and restrictions for clock and data signals. Identify FPGA interfacing resources. Utilize the I/O resources in your design. Describe the combining of different I/O standards. Identify FPGA clocking resources. Apply the physical clocking restriction to your application.
- FPGA I/O
- Combining High-Speed I/O Standards
- High-Speed Clocks on PCB: FPGA Clock Resources
- High-Speed Clocks on PCB: Clock Generation
- High-Speed Clocks on PCB: Clock Distribution
- High-Speed Clocks on PCB: Board Deskewing
- DDR3 Memory Interfacing
Signal Interfacing – Part B: FPGA-Specific Interfacing
Objective: Describe typical FPGA I/O special standards. Use FPGA interface resources for board design.
- I/O Standards
- On-Chip Termination
- Banking Rules
- Serial I/O (Data and Clock Pins)
- XADC I/O (Analog Inputs)
- Simultaneous Switching Outputs
- Lab 5: I/O Pin Planning
Die and Package
Objective: Use the relationship between chip pad locations and package pin locations for optimal placement of external components. Identify the user pin naming conventions. Evaluate board pin placement for achieving optimum performance.
- Die and Package Relationship
- FPGA User Pin Notation
- FPGA Pin Locations Overview
- General Pin Placement Considerations
PCB Details
Objective: Review basic information about the materials and processes for PCBs. Describe how to apply the requirements for signal integrity as well as board design to the realization of the PCB through proper application of the various options for layer stackup. Describe PCB technology. Identify some PCB trace characteristics. Describe aspects of FPGA routability.
- PCB Technology
- PCB Traces
- Trace Characteristics
- Layer Stackup and Rule
- FPGA Packages and Routability
Thermal Aspects
Objective: Review basic information about the materials and processes for PCBs. Describe how to apply the requirements for signal integrity as well as board design to the realization of the PCB through proper application of the various options for layer stackup. Describe PCB technology. Identify some PCB trace characteristics. Describe aspects of FPGA routability.
- FPGA Heat Flow
- Thermal Resistance
- Thermal Resistance Calculation
- Heat Sink Selection
- Lab 6: Thermal Design
Tools for PCB Planning
Objective: Summarize helpful tools for the board design planning process such as power estimation, simulation of transmission lines, power design, simultaneously switching output (SSO), serial backplane transmission, thermal simulation.
Board Design Summary – PCB Checklist
Objective: Provide a summary of the board design part of the course such as Layers, Bypassing, Simultaneously switching output (SSO), Signal paths, Power supply and management, Design for debug.