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Programming Zynq RFSoC Using Simulink
Embedded System and FPGA Design/ SoC and MPSoC
Programming Zynq RFSoC Using Simulink
Learn to transfer data from the RFSoC to MATLAB®, implement a HDL RFSoC Design based on high-level requirements.
Complimentary Services: Post training email support & 1-hr consultation session within 1 month after the course completion!,
Course
Highlights
This hands-on, two-day course focuses on developing and configuring models in Simulink® and deploying on AMD Zynq® UltraScale+ RFSoCs.
Topics include:
- Zynq RFSoC platform overview and environment setup
- Frequency planning and Nyquist zones
- System simulation, deployment and testing of the RFSoC with the SoC Blockset
- Deployment via HW/SW co-design
Who Should
Attend
This hands-on course is designed for engineers who wish to design and simulate their system with Simulink and accelerate the implementation to Zynq SoC device using HDL Coder and Embedded Coder.
Course
Prerequisites
Knowledge of concepts of communication systems and hardware design.
Course
Benefits
Upon the completion of the course, the participants will be able to
- Setup the RFSoC
- Transfer data from the RFSoC to MATLAB®
- Implement an HDL RFSoC Design based on high-level requirements
- Deploy and interact with your FPGA design at run-time verify performance from MATLAB.
Partners
Upcoming Program
- Please keep me posted on the next schedule
- Please contact me to arrange customized/ in-house training
Course Outline
RFSoC Device Overview
Objective: Introduction to RFSoC’s device settings, parameters, and hardware details.
- Introducing Zynq RFSoC
- Reviewing RFSoC transceiver tiles
- Examining RFSoc digital up converter and down converter
- Reviewing differences between RFSoC Generation 1 and Generation 3 devices
- Reviewing the support offerings of MathWorks® for RFSoC
Frequency Planning
Objective: Provide an introduction to frequency planning with Nyquist zones and sampling rates as used with the DAC and ADC tiles in the RFSoC.
- Using the DAC tile Digital Quadrature Modulator for digital up conversion
- Using the normal mode (Nyquist Zone 1) and mixed mode (Nyquist Zone 2) operations of DAC tiles for transmission
- Applying a bandpass sampling theorem to choose a sampling rate for the receiver
Getting the model ready for the RFSoC
Objective: Simulate transmission and reception of a digital signal in the RFSoC.
- Review frame-based processing
- Simulate a transmitter and receiver model for the RFSoC
- Prepare model for deployment to the RFSoC
Target RFSoC using SoC Blockset
Objective: Simulate, model and perform analysis of SoC HW/SW architectures specifically to target gen 1,3 RFSoC.
- Introduction to SoC Blockset
- Use RFSoC template from SoC Blockset to create RFSoC system modeling framework
- Simulate and generate code for PL and PS side of algorithm using SoC Builder
- Deploy application on the board targeting FPGA, ARM and RF converter tiles
Hardware Software Co-design for RFSoC
Objective: Deploy and interact with your HDL IP design at run-time verify performance from MATLAB.
- Generate and examine the RFSoC Vivado project
- Access streaming and parameter data of the generated HDL IP at run-time
- Dynamically configure RF Data Converter settings in MATLAB