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FPGA Resource Reuse Zero to Expert
FPGA Resource Reuse Zero to Expert
This training course offer experience how to construct filter design with Vitis model composer, implement, and download a Dynamic Function eXchange(DFX) FPGA design using the Vivado™ Design Suite. This course covers both the tool flow and mechanics of successfully creating a DFX design.
Course
Highlights
This three-day course provides experience with:
- Creating a model-based design using HDL library blocks along with custom blocks in Vitis Model Compose
- Implementing DSP functions using Vitis Model Composer
- Identifying best design practices and understanding the subtleties of the DFX design flow
- Using DFX in the AMD FPGAs and adaptive SoCs
- Using the DFX Controller and DFX Decoupler IP in the DFX process
- Implementing DFX in an embedded system environment
- Applying appropriate debugging techniques on DFX designs
- Employing best practice coding styles for a DFX system
Hands-on Project (1-day) allows you to test your knowledge and apply your skills immediately. No documentation, no labs instructions, you will face the real challenge to do a full FPGA design flow project with the guidance of our instructor
Who Should
Attend
Digital designers who have a working knowledge of HDL (VHDL or Verilog) and digital design and who want to implement Dynamic Function eXchange techniques.
Course
Prerequisites
- Basic experience with the MATLAB and Simulink software
- Basic knowledge of VHDL or Verilog
- Experience with the Vivado Design Suite
Course
Benefits
After completing this comprehensive training, you will have the necessary skills to:
- Create, simulate, and debug a Vitis Model Composer design in the Simulink environment using HDL block libraries
- Use DSP blocks in Vitis Model Composer to implement DSP functions
- Describe what Dynamic Function eXchange is
- Define DFX regions and reconfigurable modules with the Vivado Design Suite
- Generate the appropriate full and partial bitstreams for a DFX design
- Use DFX feature for the Versal devices
- Implement a nested DFX design
- Enable the Abstract Shell feature in project mode
- Use the ICAP and PCAP components to deliver partially reconfigurable systems
- Implement a DFX system using the DFX Controller IP
- Use the block design container feature of the Vivado IP integrator to create a DFX design
- Identify how Dynamic Function eXchange affects various silicon resources, including block RAM, IOBs, fabric, and MGTs
- Implement a Dynamic Function eXchange system using the following techniques:
– Direct JTAG connection, floorplanning, and timing constraints and analysis - Debug a DFX design using the Vivado Design Suite
- Implement a DFX system in an embedded environment using the Vitis Unified IDE
Partners
Upcoming Program
- Please keep me posted on the next schedule
- Please contact me to arrange customized/ in-house training
Course Outline
Introduction to Vitis Model Composer
- Introduction to Vitis Model Composer
Introduces the Vitis Model Composer tool and describe the optimized HDL, HLS, and AI Engine library blocks available in Vitis Model Composer. - Basics of the Simulink Environment
Describes the Simulink software environment, some of the commonly used signal source and sink blocks available in the Simulink software, and how hierarchical designs are created and protected using masked subsystems.
Vitis Model Composer for HDL
- HDL Library in Vitis Model Composer
Illustrates how the HDL library can be used in Vitis Model Composer and how to analyze performance and resource usage in Vitis Model Composer. - HDL Library Compilation and Hardware Co-Simulation
Covers how to import HDL modules as well as perform HDL co-simulation and hardware verification. Reviews the compilation types for Vitis Model Composer designs. Also introduces Super Sample Rate (SSR) blocks in Vitis Model Composer. - DSP Blocks in Vitis Model Composer
Describes the DSP blocks in the HDL and AI Engine library. Also reviews the basics of AXI4 interfaces. - Working with Filter Designs
Describes the concept of designing filters supported by Vitis Model Composer. - Working with Multi-Rate Systems
Explains how a multi-rate DSP system uses multiple sampling rates within a system.
Basics of DFX
- Introduction to Dynamic Function eXchange (DFX)
Explains what a Dynamic Function eXchange is and defines the terminologies used in DFX. Also provides an overview of the configuration and reconfiguration processes.
DFX Tool Flow
- DFX Flow Using the Vivado Design Suite GUI
Illustrates the steps for creating a DFX project in the Vivado Design Suite and describes various supported and unsupported features. - DFX Flow Using the Vivado Design Suite Tcl Commands
Reviews the flow using non-project-based commands, including using implementation constraints and specific characteristics. - DFX for the Versal Architecture
Describes the DFX feature for the Versal devices, explains the DFX for Network on Chip (NoC), and illustrates the NoC topologies supported in the DFX design flow. - Nested DFXRTL-to-bitstream design flow
Describes using nested DFX, the process by which a Reconfigurable Partition (RP) can be segmented into smaller regions, each of which is partially reconfigurable. - Abstract Shell for Dynamic Function eXchange
Describes how compilation time can be reduced by using an Abstract Shell.
DFX Design Considerations for AMD Devices
- DFX Design Considerations for All AMD Devices
Covers the requirements, characteristics, and limitations associated with the DFX designs that can simplify the debug process and reduce the risk of design malfunctions. - DFX Design Considerations for 7 Series, Zynq SoC, UltraScale, and UltraScale+ Devices
Discusses the DFX design consideration methodologies for various AMD device families. - DFX Design Considerations for Versal Devices
Describes the DFX design requirements that are specific to the Versal devices.
DFX Design-Specific IP Blocks
- DFX Intellectual Property (IP)
Reviews the various IPs that are specifically for use with the DFX designs. - DFX Block Design Containers in IP Integrator
Describes the block design container feature and how BDCs enable DFX.
DFX Configuration
- Configuring Devices Using DFX(IP)
Reviews the basics of configuration and various configuration modes. - Configuration Parameters
Covers various configuration parameters, including factors that affect configuration time and configuration debugging. - DFX Bitstreams and PDIs(IP)
Describes the different types of bitstreams for the DFX compilation, including full, partial, blanking, and clearing. Also explains partial programmable device image (PDI) for the Versal™ devices. - DFX Bitstream Integrity
Describes partial bit file integrity and implementing a DFX through the ICAP for the FPGA devices.
DFX Design Analysis and Debugging
- Floorplanning a DFX Design
Demonstrates how to create Pblocks for various devices and how to create a floorplan for a reconfigurable region. - Floorplanning for Versal Devices
Illustrates floorplanning methodologies for Versal devices and explains challenges in the Versal floorplanning. - DFX Timing Analysis and Constraints
Illustrates how and when to apply different constraint files, the process of performing a DFX timing-level simulation, and the process of performing static timing analysis on a DFX design. - DFX Debugging
Illustrates the DFX debugging techniques using the Vivado Design Suite debug cores.
DFX Designs in Embedded Systems
- DFX in Embedded Systems
Describes the embedded design flow in the Vivado Design Suite, the advantages of using a processor with a DFX, and how to connect a processor to the PCAP to control a DFX using the Vitis Unified IDE. - DFX Designs Using the PCIe Core
Reviews the advantages of using a PCIe core in a DFX design.
