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Embedded Systems Design
Learn general embedded concepts, tools, and techniques using the
Vivado® Design Suite and Vitis™ unified software platform.
Course
Highlights
This two-day training let you Learn general embedded concepts, tools, and techniques using the Vivado® Design Suite and Vitis™ unified software platform.
The emphasis is on:
- Designing, expanding, and modifying embedded systems utilizing
the features and capabilities of the Zynq® System on a Chip (SoC), Zynq UltraScale+™ MPSoC, or MicroBlaze™ soft processor - Adding and simulating AXI-based peripherals using bus functional
model (BFM) simulation
What’s New for 2021.2
- All labs have been updated to the latest software versions
Who Should
Attend
Engineers who are interested in developing embedded systems with the Xilinx Zynq SoC, Zynq UltraScale+ MPSoC, and/or MicroBlaze soft processor core.
Course
Prerequisites
- FPGA design experience
- Completion of the Designing FPGAs Using the Vivado Design Suite 1 course or equivalent knowledge of Xilinx Vivado software implementation tools
- Basic understanding of C programming
- Basic understanding of microprocessors
- Some HDL modeling experience
Course
Benefits
After completing this comprehensive training, you will have the
necessary skills to:
- Describe the various tools that encompass a Xilinx embedded design
- Rapidly architect an embedded system containing a Cortex-A9/A53/R5 or MicroBlaze processor using the Vivado IP integrator and Customization Wizard
- Develop software applications utilizing the Vitis unified software
platform - Create and integrate an IP-based processing system component in the Vivado Design Suite
- Design and add a custom AXI interface-based peripheral to the
embedded processing system - Simulate a custom AXI interface-based peripheral using
verification IP (VIP)
Partners
Upcoming Program
- Please keep me posted on the next schedule
- Please contact me to arrange customized/ in-house training
Course Outline
Embedded UltraFast Design Methodology
Objective: Outlines the different elements that comprise the Embedded Design Methodology.
- Enumerate the different elements that comprise the Embedded Design Methodology
- Identify the flows for both hardware and software development
Overview of Embedded Hardware Development
Objective: Overview of the embedded hardware development flow.
- Describe different flows for developing the hardware for an embedded Xilinx system
- Enumerate diagnostic approaches for validating and debugging an embedded Xilinx system
Driving the IP Integrator Tool
Objective: Describes how to access and effectively use the IPI tool.
- Describe the benefits of using the IPI tool
- Enumerate some of the differences between a traditional development flow and one using the IPI tool
Overview of Embedded Software Development
Objective: Reviews the process of building a user application.
- Describe the primary software development environment used with Xilinx devices
- List some of the Xilinx-provided extensions available in the Vitis™ IDE
- Enumerate some of the under-the-hood tools provided in the Vitis IDE
Driving the Vitis Software Development Tool
Objective: Introduces the basic behaviors required to drive the Vitis tool to generate a debuggable C/C++ application.
- Describe the purpose of the Vitis™ integrated design environment (IDE)
- Enumerate some of the Xilinx extensions provided in the Vitis IDE
- List the primary capabilities offered in the Vitis IDE
AXI: Introduction
Objective: Introduces the AXI protocol.
- Describe how AXI fits into the AMBA protocol developed by Arm
- Explain what AXI is and what it is not
AXI: Variations
Objective: Describes the differences and similarities among the three
primary AXI variations.
- Describe the differences & similarities among the three primary AXI variations
AXI: Transactions
Objective: Describes the differences and similarities among the three
primary AXI variations.
- Describes different types of AXI transactions.
Introduction to Interrupts
Objective: Explain the difference between an interrupt and an exception.
- Describe the basic behavior of an interrupt-driven system
- Explain the difference between an interrupt and an exception
Explain the difference between an interrupt and an exception
Objective: Reviews the hardware that is typically available to help implement and manage interrupts.
- Identify the different types of interrupt controllers available in Xilinx devices
- Explain how interrupt controllers operate
AXI: Connecting AXI IP
Objective: Describes the relationships between different types of AXI interfaces and how they can be connected to form hierarchies.
- Describe the basic differences between AXI3 and AXI4 and their management within the Xilinx tools
- Explain how IPI interfaces aid in making connections
- Identify basic IP for creating full AXI hierarchies
Creating a New AXI IP with the Wizard
Objective: Explains how to use the Create and Import Wizard to create and package an AXI IP.
- Use the Create and Package IP Wizard to convert an existing IP into an AXI-compatible form
- Use the Create and Package IP Wizard to package new IP
AXI: BFM Simulation Using Verification IP
Objective: Describes how to perform BFM simulation using the Verification IP.
- Explain what is the importance of BFM
- Explain how the BFM works
MicroBlaze Processor Architecture Overview
Objective: Overview of the MicroBlaze microprocessor architecture.
- Enumerate the main components comprising the MicroBlaze™ processor, including the interrupt vector table, interfaces, and cache structure
- Describe the common supporting IP used with the MicroBlaze processor pertaining to resets and clocks, the memory subsystems, and debugging
MicroBlaze Processor Block Memory Usage
Objective: Highlights how block RAM can be used with the MicroBlaze processor.
- Explain how block RAM can be used with the MicroBlaze™ processor
Zynq-7000 SoC Architecture Overview
Objective: Overview of the Zynq-7000 SoC architecture.
- Describe the high-level blocks contained within Zynq®-7000 SoC devices
- Describe the connections among the high-level blocks and between the processing system (PS) and programmable logic (PL)
Zynq UltraScale+ MPSoC Architecture Overview
Objective: Overview of the Zynq UltraScale+ MPSoC architecture.
- Identify the major functional components of the Zynq® UltraScale+™ MPSoC
- Describe the power management strategy
