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Designing with Xilinx Serial Transceivers
Connectivity Design
Designing with Xilinx Serial Transceivers
Learn how to employ serial transceivers in UltraScale and UltraScale+ FPGA designs or Zynq UltraScale+ MPSoC designs
Course
Highlights
The focus of this two-day training is on:
- Identifying and using the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection
- Utilizing the Transceivers Wizards to instantiate transceiver primitives
- Synthesizing and implementing transceiver designs
- Taking into account board design as it relates to the transceivers
- Testing and debugging
Who Should
Attend
This hands-on course is designed for FPGA Designers and logic designers.
Course
Prerequisites
- Verilog experience (or the Designing with Verilog or the Designing with VHDL course)
- Familiarity with logic design (state machines and synchronous design)
- Basic knowledge of FPGA architecture and Xilinx implementation
tools are helpful - Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful
Course
Benefits
After completing this comprehensive training, you will have the
necessary skills to:
- Describe and use the ports and attributes of the serial transceivers in Xilinx FPGAs and MPSoCs
- Effectively use the following features of the gigabit transceivers:-
- 64B/66B and other encoding/decoding, comma detection, clock correction, and channel bonding
- Pre-emphasis and receive equalization
- Use the Transceivers Wizards to instantiate GT primitives in a
design - Access appropriate reference material for board design issues
involving signal integrity and the power supply, reference
clocking, and trace design - Use the IBERT design to verify transceiver links on real hardware
Partners
Upcoming Program
- Please keep me posted on the next schedule
- Please contact me to arrange customized/ in-house training
Course Outline
UltraScale FPGA Transceivers Overview
Objective: Provide an overview of the GT transceivers in UltraScale™ FPGAs. Describe the main features of the serial transceiver, the GT_QUAD tile, the GT transmitter architecture and functionality, the GT receiver architecture and functionality.
- UltraScale Architectures GT Solutions
- GT Tile
- GT Transmitter
- GT Receiver
- Ease of Use
UltraScale FPGA Transceivers Clocking and Resets
Objective: Describe the sources for transceiver reference clock signals and how to set the PLL attributes to create transceiver clocks. User clocks and reset signals are also described. Identify the three possible sources for GT reference clock signals. Set the PLL attributes to create internal GT clocks. Define each of the user clocks and their specific functions.
- Reference Clocks
- PLLs in the GT QUADs
- TX Phase Interpolator
- User Clocks
- Resets
Transceivers Wizard
Objective: provide an overview of the 7 Series and UltraScale™ FPGA Transceivers Wizard. Describe the features of the Transceivers Wizard. Use the Transceivers Wizard to configure and instantiate GT primitives in an HDL design. Explain the usage of the transceiver IP example design.
- Transceivers Wizard Usage Options
- Transceivers Wizard
- Using the Example Design
- Transceiver Integration in User Design
- Lab 1: Transceiver Core Generation
Transceiver Simulation
Objective: Describe the processes for simulating a design with serial transceivers. Describe simulation options. Compile serial transceiver models for simulation. Describe how to perform transceiver design simulation.
- Simulation Options and Preparation
- Performing Simulation
- Lab 2: Transceiver Simulation
Transceiver PCS Layer Details: Part 1 - Basic Blocks
Objective: Discuss the Transceiver PCS Layer details for 7 series and UltraScale™ FPGAs. Describe the main features of PCS blocks. Describe the transceiver PCS functionality. Describe the usage options of PCS layer blocks.
- Fabric Interface
- Byte and Word Alignment
- RX Elastic Buffer
- Clock Correction
- Channel Bonding
Transceiver PCS Layer Details - Part 2: Encoding Options
Objective: Discuss the Transceiver PCS Layer details for 7 series and UltraScale™ FPGAs. Describe the main features of PCS blocks. Describe the transceiver PCS functionality. Describe the usage options of PCS layer blocks.
- 8B/10B Encoding
- 64B/66B Encoding
- 64B/67B Encoding
- Synchronous Gearboxes
- Asynchronous Gearboxes
- 128B/130B Encoding
- Lab 3: 64B/66B Encoding
Transceiver Implementation
Objective: Describe the processes for implementing a design with serial transceivers. List the guidelines for channel bonding placement. Write timing constraints for serial transceiver clocks. Implement a design containing serial transceivers. Change serial transceiver attributes in the Device Viewer.
- Implementation Considerations
- Software Flow
- Vivado IP Packager
- Lab 4: Transceiver Implementation
PMA Layer Details
Objective: Describe special features for transmitting and receiving for the physical media attachment layer. Describe the special features of the transceiver TX PMA layer. Describe the special features of the transceiver RX PMA layer. List the parameters for optimizing a transceiver link.
- TX Polarity Control and PISO
- TX Driver
- RX Termination and Equalization
- RX CDR
- RX SIPO and Polarity Control
PMA Layer Optimization
Objective: Describe options to validate and optimize the PMA layer parameters. Identify the possibilities for link optimization. Use various integrated bit error ratio test (IBERT) options to validate serial transceiver links.
- IBERT Design
- In-System IBERT IP
- Options and Strategies for Link Setup
- Lab 5: IBERT Design
Transceiver Test and Debugging
Objective: Cover transceiver testing and debugging in 7 series and UltraScale™ FPGAs. Identify the possibilities for serial transceiver test and debugging. Use transceiver internal test options. Use debug cores for transceiver test and debug. Describe hardware measurement options.
- Loopback
- Built-in PRBS Options
- Using Vivado Debug Cores
- Measurement Options
- Lab 6: Transceiver Debugging
Transceiver Board Design Considerations
Objective: Describe the power requirements of the GT transceiver, lists some guidelines for trace routing and signal integrity, and explains the need for GT link simulation on the board level. Describe the power requirements of the GT transceiver. List some guidelines for trace routing and signal integrity.
- Transceiver Board Interface
- Transceiver Board Design
- Transceiver Signal Integrity
Transceiver Application Examples
Objective: Describe how serial transceivers apply to special applications, focusing on Aurora, Networking IPs, Interlaken, PCI Express®, and JESD204 technologies. Describe main serial transceiver applications. Use the serial transceiver in application specific IPs.
- Aurora
- Networking
- Interlaken
- PCI Express Technology
- JESD204