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Designing with UltraScale FPGA Transceivers
Connectivity Design
Designing with UltraScale FPGA Transceivers
Learn how to employ serial transceivers in your UltraScale™ FPGA design.
Course
Highlights
This two-day course help you to learn how to employ serial transceivers in your UltraScale™ FPGA design. Understand and utilize the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection.
Additional topics include use of the UltraScale FPGAs Transceiver Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.
Who Should
Attend
FPGA designers and logic designers.
Course
Prerequisites
- Verilog or VHDL experience or the Designing with Verilog or Designing with VHDL course
- Familiarity with logic design (state machines and synchronous design)
- Basic knowledge of FPGA architecture and Xilinx implementation tools are helpful
- Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful
Course
Benefits
After completing this comprehensive training, you will know how to:
- Describe and utilize the ports and attributes of the serial transceiver in UltraScale FPGAs
- Effectively utilize the following features of the gigabit transceivers:
- 64B/66B and other encoding/decoding, comma detection, clock correction, and channel bonding
- Pre-emphasis and linear equalization
- Use the UltraScale FPGAs Transceivers Wizard to instantiate GT primitives in a design
- Access appropriate reference material for board design issues involving signal integrity and the power supply, reference clocking, and trace design
- Use the IBERT design to verify transceiver links on real hardware
Partners
Upcoming Program
- Please keep me posted on the next schedule
- Please contact me to arrange customized/ in-house training
Course Outline
UltraScale Architecture Overview
Objective: summarizes all of the new features and hard IP in the UltraScale™ FPGAs.
- CLB and Clocking Improvementss
- Block-Level Innovations
UltraScale FPGA Transceiver Overview
Objective: provides an overview of the GT transceivers in UltraScale™ FPGAs.
- UltraScale FPGA GT Solution
- GT Tile, Transmitter, Receiver
- Standards Support
UltraScale FPGA Transceiver Clocking and Resets
Objective: describes the sources for transceiver reference clock signals and how to set the PLL attributes to create transceiver clocks. User clocks and reset signals are also described.
- PLLs in the GT QUADs
- TX Phase Interpolator
- User Clocks
- Resets
UltraScale FPGAs Transceivers Wizard
Objective: provides an overview of the UltraScale™ FPGAs Transceivers Wizard.
- Transceiver Wizard Usage Options
- Transceiver Wizard
- Using the Example Design
- Including the Transceiver in Your Design
- Lab 1: Transceiver Core Generation – Use the UltraScale FPGAs Transceivers Wizard to create instantiation templates
Transceiver Simulation
Objective: describes the processes for simulating a design with serial transceivers.
- Simulation Options and Preparation
- Performing Simulation
- Lab 2: Transceiver Simulation – Simulate the transceiver IP by using the IP example design
PCS Layer General Functionality
Objective: discusses the Transceiver PCS Layer details for UltraScale™ FPGAs.
- Fabric Interface
- Byte and Word Alignment
- RX Elastic Buffer
- Clock Correction
- Channel Bonding
PCS Layer Encoding
Objective: discusses the Transceiver PCS Layer coding options for UltraScale™ FPGAs.
- 8B/10B Encoding
- 64B/66B Encoding
- 64B/67B Encoding
- Synchronous Gearboxes
- Asynchronous Gearboxes
- 128B/130B Encoding
- Lab 3: 64B/66B Encoding – Generate a 64B/66B transceiver core by using the UltraScale FPGAs Transceivers Wizard, simulate the design, and analyze the results
Transceiver Implementation
Objective: describes the processes for implementing a design with serial transceivers.
- Software Flow
- Vivado IP Packager
- Lab 4: Transceiver Implementation – Implement the transceiver IP by using the IP example design
PMA Layer Details
Objective: describes special features for transmitting and receiving for the physical media attachment layer.
- TX Polarity Control and PISO
- TX Driver
- RX Termination and Equalization
- RX CDR
- RX SIPO and Polarity Control
Transceiver Board Design Considerations
Objective: describes the power requirements of the GT transceiver, lists some guidelines for trace routing and signal integrity, and explains the need for GT link simulation on the board level.
- Transceiver Board Interface
- Transceiver Board Design
- Transceiver Signal Integrity
Transceiver Test and Debugging
Objective: covers transceiver testing and debugging in UltraScale™ FPGAs.
- Loopback
- Built-in PRBS Options
- Using Vivado Debug Cores
- IBERT Design
- Measurement Options
- Options and Strategies for Link Setup
- Lab 5: IBERT Design – Verify transceiver links on real hardware
Transceiver Application Examples
Objective: describes how serial transceivers apply to special applications, focusing on Aurora, Networking IPs, Interlaken, PCI Express®, and JESD204 technologies.
- Networking
- Interlaken
- PCI Express Technology
- JESD204B