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Design Timing Closure Zero to Expert
Design Timing Closure Zero to Expert
Learn the fundamental of the static timing analysis (STA), follow by how to achieve design closure more efficiently and tackle hard timing challenges.
Course
Highlights
This three-day provides experience with:
- Understand STA concept
- Generating and downloading a bitstream onto a demo board
- Applying initial design checks and reviewing timing summary and methodology reports for a design
- Using baselining to verify that a design meets timing goals and applying the guidelines described in the baselining process
- Identifying and resolving setup and hold violations
- Reducing logic delays, net delays, and congestion in a design
- Applying basic timing constraints
- Improving clock skew and clock uncertainty
- Performing Pblock-based and super logic region (SLR) based analysis to identify challenges and improve timing closure
- Performing quality of results (QoR) assessments at different stages to improve the QoR score
- Implementing intelligent Design Runs (IDR) to automate analysis and timing closure for complex desigh
Hands-on Project on the last day allows you to test your knowledge and apply your skills immediately. No documentation, no labs instructions, you will face the real challenge to do a full FPGA design flow project with the guidance of our instructor
Who Should
Attend
Software and hardware developers, system architects, and anyone who wants to learn about design closure techniques.
Course
Prerequisites
- Basic knowledge of the VHDL or Verilog language
- Digital design knowledge
Course
Benefits
After completing this comprehensive training, you will have the necessary skills to:
- Apply clock and I/O timing constraints and perform timing analysis
- Describe the “baselining” process to gain timing closure on a design
- Describe what is design closure as well as its three pillars
- Resolve setup and hold violation by reducing logic delay and net delay
- Improve clock skew and clock uncertainty
- Identify clock domain crossing (CDC) and scenarios that require synchronization circuits
- Perform QoR assessment at different stages and improve the QoR scor
- Implement intelligent DesignRuns (IDR)
Partners
Upcoming Program
- Please keep me posted on the next schedule
- Please contact me to arrange customized/ in-house training
Course Outline
Introduction to FPGA Architecture, 3D ICs, SoCs, ACAPs
Objective: Overview of FPGA architecture, SSI technology, and SoC device architecture.
- FPGA architecture
- major building blocks of FPGAs
- stacked silicon-based 3D IC devices
- SoC devices
- Describe Adaptive Compute Acceleration Platforms (ACAPs)
Introduction to Vivado Design Flows
Objective: Introduces the Vivado design flows: the project flow and non-project batch flow.
- various design flows in the Vivado® Design Suite
- RTL-to-bitstream design flow
- supported use models in the Vivado Design Suite
- system-level integration flows
Introduction to Clock Constraints
Objective: Apply clock constraints and perform timing analysis.
- what is a clock
- appropriate clock constraints for your design
- input jitter and clock latency
- clocks present in the design
Generated Clocks
Objective: Use the report clock networks report to determine if there are any generated clocks in a design.
- generated clocks
- automatically and manually generated clocks
- relationship between a generated clock and the source clock
Timing Constraints Wizard
Objective: Use the Timing Constraints Wizard to apply missing timing constraints in a design.
- Timing Constraints Wizard to create timing constraints
- completion of timing constraints using the Timing Constraints Wizard
Basics of Clock Gating and Static Timing Analysis
Objective: Describes the basics of clock gating and static timing analysis.
- basics of clock gating
- basics of static timing analysis
- setup and hold slack
Calculating Setup and Hold Timing
Objective: Reviews setup and hold timing calculations.
- setup and hold slacks
- input setup and hold analysis
- output setup and hold analysis
Timing Closure
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Introduction to UltraFast Design Methodology Timing Closure
- Provides an overview of the various stages of the UltraFast Design Methodology for timing closure.
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Baselining
- Demonstrates the performance baselining process, which is an iterative approach to incrementally constrain a design and meet timing.
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Setup and Hold Violation Analysis
- Covers what setup and hold slack are and describes how to perform input/output setup and hold analysis.
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Reducing Logic Delay
- Describes how to optimize regular fabric paths and paths with dedicated blocks and macro primitives.
Timing Closure (continued)
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Reducing Net Delay
- Reviews different techniques to reduce congestion and net delay. Improving Clock Skew Describes how to apply various techniques to improve clock skew.
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Improving Clock Skew
- Describes how to apply various techniques to improve clockskew
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Improving Clock Uncertainty
- Reviews various flows for improving clock uncertainty, including using parallel BUFGCE_DIV clock buffers, changing MMCM or PLL settings, and limiting synchronous clock domain crossing (CDC) paths.
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Clock Domain Crossing (CDC) and Synchronization Circuits
- Explains what clock domain crossings (CDC) are and the scenarios that require synchronization circuits.
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QoR Reports Overview
- Describes what quality of result (QoR) is and how to analyze the QoR reports generated by the Vivado IDE.
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Intelligent Design Runs (IDR)
- Introduces Intelligent Design Runs (IDR), which are special types of implementation runs that use a complex flow to attempt to close timing.