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Advanced Features and Techniques of Embedded Systems Design
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Advanced Features and Techniques of Embedded Systems Design
Learn how to use advanced components of embedded systems design for architecting a complex system in the Zynq System on a Chip (SoC) or MicroBlaze™ soft processor
Course
Highlights
The emphasis of this two days course is on:
- Developing, debugging, and simulating an embedded system
- Utilizing memory resources
- Implementing high-performance DMA
- Improving designs by using the Vivado IP Integrator
- Demo boards in which designs are downloaded and verified
Who Should
Attend
Hardware, firmware, and system design engineers who are interested in Xilinx embedded systems development flow
Course
Prerequisites
- Embedded Systems Development course or experience with
embedded systems design and the Vivado Design Suite - Basic C programming
- Working knowledge of the Zynq SoC (Cortex™-A9 processor), Zynq UltraScale+ MPSoC processors (Cortex-A53 or Cortex-R5 processors), or MicroBlaze processor
Course
Benefits
After completing this comprehensive training, you will have the necessary skills to:
- Assemble an advanced embedded system
- Take advantage of the various features of the Zynq SoC, Zynq UltraScale+ MPSoC, and Cortex and MicroBlaze processors, including the AXI interconnect, and the various memory
controllers - Apply advanced debugging techniques, including the use of the Vivado logic analyzer tool for debugging an embedded system and HDL system simulation of processor-based designs
- Integrate an interrupt controller and interrupt handler into an embedded design
- Design a flash memory-based system and boot load from off-chip flash memory
- Perform HDL-based system simulation
Partners
Upcoming Program
- Please keep me posted on the next schedule
- Please contact me to arrange customized/ in-house training
Course Outline
Overview of Embedded Hardware Development
Objective: Provides an overview of embedded hardware development.
Hardware-Software Flow
Objective: Illustrates how design information generated during the hardware development process is moved into the SDK tool realm.
Software Overview
Objective: Provides a thorough understanding of how the integrated design environment works, including how the compiler and linker behave, basics of makefiles, DMA usage, and variable scope.
- tools that compose the development environment – Front-end versus back-end toolchains and cross-compilation
- how memory and DMA relate
- C-specific concepts relevant to acceleration concepts
Zynq-7000 All Programmable SoC Architecture Overview
Objective: Overview of the Zynq7000 SoC architecture.
MicroBlaze Processor Architecture Overview
Objective: Overview of the MicroBlaze microprocessor architecture.
Zynq UltraScale+ MPSoC Overview
Objective: Overview of the Zynq UltraScale+ MPSoC architecture.
Debugging Hardware Introduction
Introduces the need and offers a solution for in-chip testing of hardware designs.
Debugging Hardware - Marking Nets
Objective: Reviews the process of marking nets to show which signals should be monitored without having to explicitly instantiate ILA cores.
Hardware-Software Co-Debugging g (Cross-Triggering)
Objective: Describes how to enable events in hardware to pause the software execution and breakpoints in software to cause an ILA trigger.
Memory Types
Objective: Provides a brief overview of the different types of memory available, as well as when one type of memory would be selected over another.
Block RAM Controllers
Objective: – Introduces two versions of block RAM controllers and how and why they are needed.
Static Memory Controllers
Objective: Discusses static memory controllers in general and the SMC implementation in the Zynq-7000 family of devices.
DDRx Memory Operation
Objective: Provides additional details regarding how DDRx memory interfaces with a controller.
Dynamic Memory Controller (Zynq-7000 Device)
Objective: Covers how the DMC is implemented as well as many of its key behaviors.
Introduction to Interrupts
Objective: Introduces the concept of interrupts, basic terminology, and generic implementation.
Interrupts and the Zynq-7000 Device
Objective: – Presents the details of how the Zynq-7000 platform uses interrupts from both a hardware and software perspective.
General Interrupt Controller
Objective: Introduces the general interrupt controller (GIC), its features, and some examples of its use.
Interrupts and the MicroBlaze Processor
Objective: Describes how interrupts are handled within the MicroBlaze processor system from a hardware perspective.
AXI Interrupt Controller for the MicroBlaze Processor
Objective: Introduces the AXI Interrupt Controller, which augments the MicroBlaze processor’s interrupt capabilities by managing multiple interrupt sources.
AXI Streaming: Introduction
Objective: – Provides the context and background for the the streaming configuration of the AXI protocol.
MicroBlaze Processor Streaming Ports
Objective: Describes and illustrates how data streaming is performed using the MicroBlaze processor.
AXI Streaming FIFO
Objective: Introduces the AXI Streaming FIFO and its capabilities.
Connecting AXI IP
Objective: Focuses on the relationships between different types of AXI interfaces and how they can be connected to form hierarchies.
DMA
Objective: Introduces various IP that supports DMA and DMA-like functionality.
Zynq-7000 Device PS-PL Interface
Objective: Discusses the various connection points between the PS and PL.
High-Speed: USB
Objective: Introduces the USB high-speed peripheral.
High-Speed: Gigabit Ethernet
Objective: Introduces the Gigabit Ethernet high-speed peripheral.
Low-Speed: Overview
Objective: Introduces the low-speed peripherals in the Zynq SoC.
Low-Speed: CAN
Objective: Introduces the CAN low-speed peripheral.
Low-Speed: I2C
Objective: Introduces the I2C low-speed peripheral.
Low-Speed: SD/SDIO
Objective: Introduces the SD/SDIO low-speed peripheral.
Low-Speed: SPI
Objective: Introduces the SPI low-speed peripheral.
Low-Speed: UART
Objective: Introduces the UART low-speed
peripheral.
Utility Logic
Objective: Covers the IP that provides basic logic support within the block design.
Sharing PS Resources (Hardware Perspective)
Objective: Illustrates from the hardware design perspective how a master in the PL can leverage resources within the PS.
Multi-Processor Hardware Architecture
Objective: Addresses some of the mechanisms that a designer can leverage to support cross processor communications.
Caching
Objective: – Introduces the concept of caching and describes how this technique is implemented using the Xilinx processor systems.
Processor Caching and SCLR
Objective: Introduces the concepts behind processing caching and the System-Level Control Register.
Accelerator Coherency Port
Objective: Describes the purpose and general behavior of the accelerator coherency port (ACP).
Booting Flow
Objective: Provides a low-level view of the booting process.
Booting PL
Objective: Introduces the concepts behind configuring the PL at boot.
Booting Flash Image Generation
Objective: Introduces the Flash Image Generator tool, which is used to collect up a variety of files and order them properly in the Flash so that the FSBL can correctly read them.
QEMU: Introduction
Objective: Introduction to the Quick Emulator, which is the tool used to run software for the Zynq device when hardware is not available.