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Embedded System Design with ADC/DAC
Learn general embedded concepts, tools, and techniques using the
Vivado® Design Suite and Vitis™ unified software platform with a special emphasis on the RF Data Converter
Course
Highlights
This four-day training let you Learn general embedded concepts, tools, and techniques using the Vivado® Design Suite and Vitis™ unified software platform.
The emphasis is on:
- Designing, expanding, and modifying embedded systems utilizing the features and capabilities of the Zynq UltraScale+™ MPSoC.
- Adding and simulating AXI-based peripherals using bus functional model (BFM) simulation
- Describing the RFSoC family in general
- Identifying applications for the RF Data Converter
- Configuring, simulating, and implementing the blocks
- Verifying the RF Data Converter on real hardware
Who Should
Attend
Engineers who are interested in developing embedded systems with the Zynq UltraScale+ MPSoC. and interested in understanding the architecture and capabilities of the Zynq UltraScale+ RFSoC data converter.
Course
Prerequisites
- FPGA design experience
- Basic understanding of microprocessors
Course
Benefits
After completing this comprehensive training, you will have the
necessary skills to:
- Describe the various tools that encompass a AMD embedded design
- Rapidly architect an embedded system containing a Cortex-A9/A53/R5 or MicroBlaze processor using the Vivado IP integrator and Customization Wizard
- Develop software applications utilizing the Vitis unified software platform
- Create and integrate an IP-based processing system component in the Vivado Design Suite
- Design and add a custom AXI interface-based peripheral to the embedded processing system
- Simulate a custom AXI interface-based peripheral using verification IP (VIP)
- Describe in general the new Zynq UltraScale+ RFSoC family
- Identify typical applications for the RF data converters
- Describe the architecture and functionality of the RF-ADC
- Utilize the RF-ADC via configuration, simulation, and implementation
- Describe the architecture and functionality of the RF-DAC
- Utilize the RF-DAC via configuration, simulation, and implementation
Partners
Upcoming Program
- Please keep me posted on the next schedule
- Please contact me to arrange customized/ in-house training
Course Outline
Embedded UltraFast Design Methodology
Objective: Outlines the different elements that comprise the Embedded Design Methodology.
- Enumerate the different elements that comprise the Embedded Design Methodology
- Identify the flows for both hardware and software development
Overview of Embedded Hardware Development
Objective: Overview of the embedded hardware development flow.
- Describe different flows for developing the hardware for an embedded AMD system
- Enumerate diagnostic approaches for validating and debugging an embedded AMD system
Driving the IP Integrator Tool
Objective: Describes how to access and effectively use the IPI tool.
- Describe the benefits of using the IPI tool
- Enumerate some of the differences between a traditional development flow and one using the IPI tool
Overview of Embedded Software Development
Objective: Reviews the process of building a user application.
- Describe the primary software development environment used with AMD devices
- List some of the AMD-provided extensions available in the Vitis™ IDE
- Enumerate some of the under-the-hood tools provided in the Vitis IDE
AXI: Introduction
Objective: Introduces the AXI protocol.
- Describe how AXI fits into the AMBA protocol developed by Arm
- Explain what AXI is and what it is not
AXI: Variations
Objective: Describes the differences and similarities among the three primary AXI variations.
- Describe the differences & similarities among the three primary AXI variations
AXI: Transactions
Objective: Describes the differences and similarities among the three primary AXI variations.
- Describes different types of AXI transactions.
Introduction to Interrupts
Objective: Explain the difference between an interrupt and an exception.
- Describe the basic behavior of an interrupt-driven system
- Explain the difference between an interrupt and an exception
Explain the difference between an interrupt and an exception
Objective: Reviews the hardware that is typically available to help implement and manage interrupts.
- Identify the different types of interrupt controllers available in Xilinx devices
- Explain how interrupt controllers operate
AXI: Connecting AXI IP
Objective: Describes the relationships between different types of AXI interfaces and how they can be connected to form hierarchies.
- Describe the basic differences between AXI3 and AXI4 and their management within the Xilinx tools
- Explain how IPI interfaces aid in making connections
- Identify basic IP for creating full AXI hierarchies
Creating a New AXI IP with the Wizard
Objective: Explains how to use the Create and Import Wizard to create and package an AXI IP.
- Use the Create and Package IP Wizard to convert an existing IP into an AXI-compatible form
- Use the Create and Package IP Wizard to package new IP
AXI: BFM Simulation Using Verification IP
Objective: Describes how to perform BFM simulation using the Verification IP.
- Explain what is the importance of BFM
- Explain how the BFM works
MicroBlaze Processor Architecture Overview
Objective: Overview of the MicroBlaze microprocessor architecture.
- Enumerate the main components comprising the MicroBlaze™ processor, including the interrupt vector table, interfaces, and cache structure
- Describe the common supporting IP used with the MicroBlaze processor pertaining to resets and clocks, the memory subsystems, and debugging
MicroBlaze Processor Block Memory Usage
Objective: Highlights how block RAM can be used with the MicroBlaze processor.
- Explain how block RAM can be used with the MicroBlaze™ processor
Zynq UltraScale+ MPSoC Architecture Overview
Objective: Overview of the Zynq UltraScale+ MPSoC architecture.
- Identify the major functional components of the Zynq® UltraScale+™ MPSoC
- Describe the power management strategy
Overview of Embedded Software Development
Objective: Enumerate some of the under-the-hood tools provided in the Vitis IDE.
- Describe the primary software development environment used with AMD devices
- List some of the Xilinx-provided extensions available in the Vitis™ IDE
- Enumerate some of the under-the-hood tools provided in the Vitis IDE
Zynq UltraScale+ MPSoC Software Environments
Objective: Describes the software development environments for Zynq UltraScale+™ MPSoCs.
- Enumerate critical differences between the Zynq®-7000 and Zynq UltraScale+™ devices
- Explain the two primary operating modes of the RPU and the standard APU Environment
- Define system virtualization and how it is realized in the Zynq UltraScale+ devices
Driving the Vitis Software Development Tool
Objective: Introduces the basic behaviors required to drive the Vitis tool to generate a debuggable C/C++ application.
- Describe the purpose of the Vitis™ integrated design environment (IDE)
- Enumerate some of the Xilinx extensions provided in the Vitis IDE
- List the primary capabilities offered in the Vitis IDE
System Debugger
Objective: Describes the basics of actually running a debugger and illustrates the most commonly used debugging commands.
- Describe the two broad categories of debugger commands: execution control and memory access
- Enumerate the most popular operations employed by the debugger
Standalone Software Platform Development and Coding Support
Objective: Covers the various software components, or layers, supplied by AMD that aid in the creation of low-level software and includes a discussion on drivers, domains, operating systems, and libraries. Also covers the basic services (libraries) available when coding in the Standalone environment.
- Identify C coding support provided in the Xilinx software development environment
- Enumerate AMD’s low-level libraries and the software layers with which they align
- Explain the purpose and utility of the board support package and its components
FAT File System for Standalone
Objective: Introduces the FAT file system (FFS) from the Standalone/Bare-metal library. The FFS provides drivers and utilities for effectively converting a region of memory into a file system.
- Discuss the capabilities of the File Allocation Table File System (FFS)
- Implement an application using the FFS
Using Linker Scripts
Objective: Overview of the purpose and typical use of a linker script.
- Describe the behavior of a linker script
- Build or customize a linker script
Migrating from SDK to the Vitis Platform
Objective: Overview of migrating existing Xilinx SDK projects to Vitis software development projects.
- Describe the need for the Vitis™ unified software platform
- Explain the differences between SDK and the Vitis IDE
- Describe how to migrate from SDK to the Vitis IDE
Introduction to Interrupts
Objective: Introduces the concept of interrupts, basic terminology, and generic implementation.
- Describe the basic behavior of an interrupt-driven system
- Explain the difference between an interrupt and an exception
Software Interrupts: Writing
Objective: Describes many of the considerations that a software coder must take into account when supporting interrupts.
- Describe common issues arising from interrupts
- Explain what an interrupt service routine must do
- Write a proper ISR
RF-ADC-Hardware
Objective: Covers the basics of RF-ADCs. Reviews RF-ADC architecture, functionality, interfaces, configuration, and driver support.
- Basics of ADCs
- Architecture
- Creating an ADC System in IP Integrator
- Interfaces
- Functionality
- IP Configuration
- Software Driver Overview
RF-DAC-Hardware
Objective: Covers the basics of RF-DACs. Reviews RF-DAC architecture, functionality, interfaces, configuration, and driver support.
- Basics of DACs
- Architecture
- Creating an DAC System in IP Integrator
- Interfaces
- Functionality
- IP Configuration
- Software Driver Overview