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Design Closure Techniques
Learn how to achieve design closure more efficiently and productively by using the three pillars of design closure (functional closure, timing closure, and power closure). Also learn how to solve functional behavior, timing, and power simultaneously to achieve faster time-to-market results.
Course
Highlights
The emphasis of this two days course is on:
- Applying initial design checks and reviewing timing summary and methodology reports for a design
- Using baselining to verify that a design meets timing goals and applying the guidelines described in the baselining process
- Identifying and resolving setup and hold violations
- Reducing logic delays, net delays, and congestion in a design
- Improving clock skew and clock uncertainty
- Performing Pblock-based and super logic region (SLR)-based analysis to identify challenges and improve timing closure
- Performing quality of results (QoR) assessments at different stages to improve the QoR score
- Implementing Intelligent Design Runs (IDR) to automate analysis and timing closure for complex design
Who Should
Attend
Software and hardware developers, system architects, and anyone who wants to learn about design closure techniques related to functional, timing, and power closure
Course
Prerequisites
- Basic knowledge of FPGA and SoC architecture and HDL coding techniques
- Basic knowledge of the Vivado® Design Suite
Course
Benefits
After completing this comprehensive training, you will have the necessary skills to:
- Describe what is design closure is as well as its three pillars
- Create a test bench and run simulation for functional verification
- Resolve setup and hold violations by reducing logic delay and net delay
- Improve clock skew and clock uncertainty
- Identify clock domain crossings (CDC) and scenarios that require synchronization circuits
- Perform QoR assessment at different stages and improve the QoR scor
- Implement Intelligent Design Runs (IDR)
- Apply the power closure flow for better time to market
- Estimate power consumption by using the Xilinx Power Estimator (XPE)
- Describe Versal ACAP power and thermal solutions
- Perform power optimization on a design
Partners
Upcoming Program
- Please keep me posted on the next schedule
- Please contact me to arrange customized/ in-house training
Course Outline
Introduction
Introduction to Design Closure
- Defines what design closure is and identifies the three pillars of design closure.
Functional Closure
HDL Coding Technique
- Covers basic digital coding guidelines used in an FPGA design.
Creating a Test Bench
- Describes the design components of a test bench, the different test bench types and how a self-checking test bench can be constructed.
Behavioral Simulation
- Describes the process of behavioral simulation and the simulation options available in the Vivado IDE.
Timing Simulation
- Simulate the design post-implementation to verify that a design works properly on hardware.
Timing Closure
Introduction to Clocking and Static Timing Analysis (STA)
- Describes the clock and its attributes, basics of clock gating, and static timing analysis (STA).
Introduction to UltraFast Design Methodology Timing Closure
- Provides an overview of the various stages of the UltraFast Design Methodology for timing closure.
Baselining
- Demonstrates the performance baselining process, which is an iterative approach to incrementally constrain a design and meet timing.
Setup and Hold Violation Analysis
- Covers what setup and hold slack are and describes how to perform input/output setup and hold analysis.
Reducing Logic Delay
- Describes how to optimize regular fabric paths and paths with dedicated blocks and macro primitives.
Reducing Net Delay
- Reviews different techniques to reduce congestion and net delay. Improving Clock Skew Describes how to apply various techniques to improve clock skew.
Improving Clock Skew
- Describes how to apply various techniques to improve clockskew
Improving Clock Uncertainty
- Reviews various flows for improving clock uncertainty, including using parallel BUFGCE_DIV clock buffers, changing MMCM or PLL settings, and limiting synchronous clock domain crossing (CDC) paths.
Timing Closure (continued)
Clock Domain Crossing (CDC) and Synchronization Circuits
- Explains what clock domain crossings (CDC) are and the scenarios that require synchronization circuits.
QoR Reports Overview
- Describes what quality of result (QoR) is and how to analyze the QoR reports generated by the Vivado IDE.
Intelligent Design Runs (IDR)
- Introduces Intelligent Design Runs (IDR), which are special types of implementation runs that use a complex flow to attempt to close timing.
Power Closure
Understanding Design Power for Better Time to Market
- Outlines the types of design power, describes the power closure flow, and identifies methods for bringing down the power of a device.
Xilinx Power Estimator Spreadsheet
- Demonstrates how to estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE.
Versal ACAP: Power and Thermal Solutions
- Discusses the power domains in the Versal ACAP as well as power optimization and analysis techniques. Thermal design challenges are also covered.
Design Power Constraints
- Describes what design power constraints are and how to use the Power Constraints Advisor tool. Power rail constraints are also covered.
Power Management Techniques
- Identifies techniques used for low power design.
Power Analysis and Optimization Using the Vivado Design Suite
- Covers how to use report power commands to estimate power consumption.
