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Designing an Integrated PCI Express System
Connectivity Design
Designing an Integrated PCI Express System
Learn how to implement a Xilinx PCI Express® core in custom
applications to improve time to market with the PCIe® core design
Course
Highlights
This two-day course provides you with the skill and knowledge on how to implement a Xilinx PCI Express® core in custom
applications to improve time to market with the PCIe® core design.
The focus is on:
- Constructing a Xilinx PCI Express system within the customer education reference design
- Enumerating various Xilinx PCI Express core products
- Identifying the advanced capabilities of the PCIe specification
This course also focuses on the AXI Streaming interconnect.
What’s New for 2020.2
- All labs have been updated to the latest software versions
Who Should
Attend
- Hardware designers who want to create applications using Xilinx IP cores for PCI Express
- Software engineers who want to understand the deeper workings of the Xilinx PCI Express solution
- System architects who want to leverage key Xilinx advantages related to performance, latency, and bandwidth in PCI Express
applications
Course
Prerequisites
- Experience with PCIe specification protocol
- Knowledge of VHDL or Verilog
- Some experience with Xilinx implementation tools
- Some experience with a simulation tool, preferably the Vivado® simulator
- Moderate digital design experience
Course
Benefits
After completing this comprehensive training, you will have the necessary skills to:
- Construct a basic PCIe system by:
- Selecting the appropriate core for your application
- Specifying requirements of an endpoint application
- Connecting this endpoint with the core
- Utilizing FPGA resources to support the core
- Simulating the design
- Identify the advanced capabilities of the PCIe specification protocol and feature set
Partners
Upcoming Program
- Please keep me posted on the next schedule
- Please contact me to arrange customized/ in-house training
Course Outline
Xilinx PCI Express Solutions
Objective: provides details about the Xilinx PCI Express® solutions.
- Generic PCIe IP Core
- 7 Series FPGA/SoC PCIe Solutions
- UltraScale Series FPGA PCIe Solutions
- UltraScale+ Series FPGA/MPSoC PCIe Solutions
- Third-Party Solutions
Connecting Logic to the Core – AXI Interface
Objective: an introduction to the AXI interface from ARM.
- Introduction to AXI
- PCIe Link and System Interface Signals
- Requester/Completer Interfaces
- Configuration Interfaces Signals
- Power Management Interface Signals
PCIe Core Customization
Objective: demonstrates how you can use the Vivado® IP catalog to produce a basic PCIe® endpoint core.
- Core Selection
- IP Configuration
- IP Configuration GUI Demonstration
- Lab 1: Constructing the PCIe Core – This lab familiarizes you with the necessary flow for generating a Xilinx Integrated PCI Express Endpoint core from the IP catalog
Packet Formatting Details
Objective: builds upon the protocol review and delves into the memory read and memory write completion details.
- General TLP Format
- Requester Request Descriptor
- Requester Completion Descriptor
- Completer Request Descriptor
- Completer Completion Descriptor
- Payload Structure
Simulating a PCIe System Design
Objective: module covers the concepts required for conducting a full simulation.
- Identifying Simulation Points
- Simulation Methods
- Using a Testbench in an Example Design
- Lab 2: Simulating the PCIe Core – This lab demonstrates the timing and behavior of a typical link negotiation using the Vivado simulator
Endpoint Application Considerations
Objective: discusses important design considerations when using a PCIe® endpoint core.
- Design Specification and Considerations
- Selecting the Appropriate Core
- Design Considerations – Control
- Specific Register Awareness
- Performance
PCI Express in Embedded Systems
Objective: discusses the use of PCI Express® IPs in embedded designs, especially in the IP Integrator.
- Vivado IP Integrator
- PCIe Block in IP Integrator
- PCIe IP in Zynq UltraScale+ Devices
- Lab 3: Using the PCI Express Core in IP Integrator – This lab familiarizes you with all the necessary steps and recommended settings to use the PCIe solutions in an IP integrator block design
Application Focus: DMA
Objective: discusses the theory and solutions for the most commonly performed PCIe® core task.
- DMA Introduction
- Xilinx DMA/Bridge Subsystem
- Partner DMA IPs
- Xilinx QDMA Subsystem for PCI Express
- Lab 4: Exploring the Xilinx DMA – This lab familiarizes you with all the necessary steps to set up and perform DMA transfers
Design Implementation and PCIe Configuration
Objective: describes the different PCIe® configuration mechanisms to meet the 120-ms PCIe core power-up requirements.
- PCIe IP Clocking and Reset
- PCIe IP Shared Logic
- Tandem Configuration
- Tandem PROM Configuration
- Tandem PCIe Configuration
- Software Flow Details
- Lab 5: Implementing the PCIe Design – This lab familiarizes you with all the necessary steps and recommended settings to turn the HDL source to a bitstream by using the Tandem configuration mode
Root Port Applications
Objective: provides an introduction the root port core and its basic capabilities and applications.
- Root Port
- Core Configuration
Debugging and Compliance
Objective: focuses on how the Vivado® logic analyzer feature can be used to monitor and, if necessary, debug the design. Other debugging options are discussed. Information about the post-design certification of the user’s design is discussed as well.
- Logical Debugging – Vivado Logic Analyzer
- Serial Debugging – IBERT Options
- Physical Layer Debug
- Transaction Layer Debug
- Debugging Tools
- Compliance Testing (Optional)
- Lab 6: Debugging the PCIe Design – This lab illustrates how to use the Vivado logic analyzer to monitor the behavior of the core and a small endpoint application for proper operation
Interrupts and Error Management
Objective: discusses the PCI Express® error management and gives an overview of interrupt options.
- PCIe Core Errors
- Error Reporting
- PCI-Compatible Error Reporting
- Advanced Error Reporting
- Interrupts
