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Designing with Versal AI Engine 2 – Graph Programming with AI Engine Kernels
Versal
Designing with Versal AI Engine 2 - Graph Programming with AI Engine Kernels
Learn to how to utilize the advanced MAC intrinsics, AI Engine library for faster development and advanced features in adaptive data flow (ADF) graph implementation.
Course
Highlights
This course describes the system design flow and interfaces that can be used for data movements in the Versal® AI Engine. It also demonstrates how to utilize the advanced MAC intrinsics, AI Engine library for faster development and advanced features in adaptive data flow (ADF) graph implementation, such as using streams, cascade stream, buffer location constraints, run-time parameterization and APIs to update and/read run-time parameters. The emphasis of this two days course is on:
- Implementing a system-level design flow (PS + PL + AIE) and the
supported simulation - Using an interface for data movement between the PL and AI
Engine - Utilizing advanced MAC intrinsics to implement filters
- Utilizing the AI Engine library for faster evelopment
- Applying advanced features for ptimizing a system-level design
Who Should
Attend
Software and hardware developers, system architects, and anyone who needs to accelerate their software
applications using Xilinx devices
Course
Prerequisites
- Comfort with the C/C++ programming language
- Software development flow
- Vitis™ software for application acceleration development flow
Course
Benefits
After completing this comprehensive training, you will have the
necessary skills to:
- Describe the system-level flow, which includes PS + PL + AIE (SW-HW-SW) designs
- Describe the supported emulation for a system-level design
- Describe the data movement between the PS, PL, and AI Engines
- Describe the implementation of the AI Engine and programmable logic
- Implement a system-level design for Versal ACAPs with the Vitis tool flow
- Utilize advanced MAC intrinsic syntax and application-specific intrinsics such as DDS and FFT
- Utilize the AI Engine DSP library for faster development
- Apply location constraints on kernels and buffers in the AI Engine array
- Apply runtime parameters to modify application behavior
- Debug a system-level design
Partners
Upcoming Program
- Please keep me posted on the next schedule
- Please contact me to arrange customized/ in-house training
Designing with Versal AI Engine 2 - Graph Programming with AI Engine Kernels
Application Partitioning on Versal ACAPs 1 (Review)
Objective: Covers what application partitioning is and how an application can be accelerated by using various compute engines in the Versal ACAP. Also describes how different models of computation (sequential, concurrent, and functional) can be mapped to the Versal ACAP.
Application Partitioning on Versal ACAPs 2
Objective: Explains how image and video processing can be targeted for the Versal ACAP by utilizing the different engines (Scalar Engine, Adaptable Engine, and Intelligent Engine). Also describes the AI engine development flow.
ACAP Data Communications 1
Objective: Describes the implementation of AI Engine and programmable logic (PL) kernels and how to implement the functions in the AI Engine that take advantage of low power.
- Vitis™ tool flow for Versal® ACAPs
- system integration that encompasses Versal AI Engines and programmable logic (PL)
- the AI Engine interface architecture
- data movement
ACAP Data Communications 2
Objective: Describes the programming model for the implementation of stream interfaces for the AI Engine kernels and PL kernels. Lists the stream data types that are supported by AI Engine and PL kernels.
- stream data types supported by Versal® AI Engine and PL kernels
- stream data types that are supported for HLS functions (PL)
- connect PL kernels and AI Engine kernels
System Design Flow
Objective: Demonstrates the Vitis compiler flow to integrate a compiled AI Engine design graph (libadf.a) with additional kernels implemented in the PL region of the device (including HLS and RTL kernels) and link them for use on a target platform. You can call then these compiled hardware functions from a host program running in the Arm® processor in the Versal device or on an external x86 processor
- how system integration occurs in Versal® devices
- terminology used in the Versal device system design flow
- Vitis™ tool emulation (HW, SW, AIE) and implementation flows for Versal devices and AI Engines
Introduction to AI Engine APIs for Arithmetic Operations
Objective: Describes the Versal AI Engine APIs for arithmetic, comparison, and reduction operations. For advanced users, describes how to implement filters using advanced intrinsics functions for various filters, such as non-symmetric FIRs, symmetric FIRs, or half-band decimators.
Versal AI Engine DSP Library Overview
Objective: Provides an overview of the available DSP library, which enables faster development and comes with ready-to-use example designs that help with using the library and tools.
- Versal® AI Engine DSP library
- components in the AI Engine DSP library
- AI Engine DSP library in your application
Advanced Graph Input Specifications 1
Objective: Learn advanced features such as using initialization functions, writing directly using streams from the AI Engine, cascade stream, core location constraints, and buffer location constraints.
- advanced graph input specifications
- large look-up tables (LUTs) to store predefined arrays, initialization functions to initialize the LUTs, streaming data and user constraints
Advanced Graph Input Specifications 2
Objective: Describes how to implement runtime parameterization, which can be used as adaptive feedback and to switch functionality dynamically.
- runtime parameterization
- kernel parameters using runtime parameterization
- synchronous and asynchronous updating of kernel parameters
- hierarchical composition of graphs
- platform port attributes
Versal AI Engine Application Debug and Trace
Objective: Shows to how to debug the AI Engine application running on the Linux OS and how to debug via hardware emulation that allows simulation of the application.
- Versal® AI Engine application simulation debugging methodology
- ktoolchain for Versal AI Engine application debugging
- AI Engine hardware support for event generation and collection
- event-based debugging is integrated in the Vitis™ IDE