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Designing with the Versal Adaptive SoC: Architecture and Methodology
Versal
Designing with the Versal ACAP:
Architecture and Methodology
Learn about Versal® ACAP architecture and design methodology.
Course
Highlights
The emphasis of this three-day course is on:
- Reviewing the architecture of the Versal ACAP
- Describing the different engines available in the Versal
architecture and what resources they contain - Utilizing the hardened blocks available in the Versal architecture
- Using the design tools and methodology provided by Xilinx to
create complex systems - Describing the network on chip (NoC) and AI Engine concepts
and their architectures - Performing system-level simulation and debugging
What’s New for 2021.2
- Updated the Versal ACAP methodology modules
- Added introduction to Versal AI Edge series
- All labs have been updated to the latest software versions
Who Should
Attend
Software and hardware developers, system architects, and anyone who wants to learn about the architecture of the Xilinx Versal ACAP device.
Course
Prerequisites
- Comfort with the C/C++ programming language
- Vitis™ IDE software development flow
- Hardware development flow with the Vivado® Design Suite
- Basic knowledge of UltraScale™/UltraScale+™ FPGAs and Zynq® UltraScale+ MPSoCs
Course
Benefits
After completing this comprehensive training, you will have the
necessary skills to:
- Describe the Versal ACAP architecture at a high level
- Describe the various engines in the Versal ACP device
- Use the various blocks from the Versal architecture to create
complex systems - Perform system-level simulation and debugging
- Identify and apply different design methodologies
Partners
Upcoming Program
- Please keep me posted on the next schedule
- Please contact me to arrange customized/ in-house training
Course Outline
Introduction
Objective: Talk about the need for Versal devices and gives an overview of the different Versal families.
- What is Adaptive Compute Acceleration Platform (ACAP)
- Significance of using Versal® ACAPs
- Various engines in a Versal ACAP device
- Different available Versal families
Architecture Overview
Objective: Provide a high-level overview of the Versal architecture, illustrating the various engines available in the Versal architecture.
- High level Versal® ACAP architecture
- Various engines in the Versal ACAP device
- NoC and memory hierarchy
Design Tool Flow
Objective: Map the various engines in the Versal architecture to the tools required and describes how to target them for final image assembly.
- Development platforms for all developers
- Vitis tool flow for Versal® devices
- Full application acceleration flow for the Vitis platform
- Toolchain for Versal AI Engine programming
Adaptable Engines (PL)
Objective: Describe the logic resources available in the Adaptable Engine.
- logic resources available in the Versal® ACAP Adaptable Engines
Processing System
Objective: Review the Cortex™-A72 processor APU and Cortex-R5
processor RPU that form the Scalar Engine. The platform
management controller (PMC), processing system manager(PSM), I/O peripherals, and PS-PL interfaces are also covered.
- Versal® ACAP processing system and its components
PMC and Boot and Configuration
Objective: Describe the platform management controller, platform loader and manager (PLM) software and boot and configuration.
- Platform management controller (PMC) architecture and interconnects in the Versal® ACAP
- Primary and secondary boot modes and sources
- Boot phases and flows
- Process for generating a boot image
SelectIO Resources
Objective: Describes the I/O bank, SelectIO™ interface, and I/O delay features.
- SelectIO resources in the Versal® ACAP
- XPHY architecture in the Versal® ACAP
- XP IOL and IOB resources
- HD IOL and IOB resources
- XPIO- and HDIO-supported standards
Clocking Architecture
Objective: Discuss the clocking architecture, clock buffers, clock routing, clock management functions, and clock de-skew.
- Clocking goals of the Versal® ACAP
- Versal ACAP clocking architecture
- Clock routing
- Clock buffers and clock management functions
- Clock deskew capabilities available in the Versal ACAP
System Interrupts
Objective: Discuss the different system interrupts and interrupt controllers.
- Different types of system interrupts in the Versal® ACAP
- System interrupt controllers
- Inter-processor interrupts
Timers, Counters, and RTC
Objective: Provide an overview of timers and counters, including the system counter, triple timer counter (TTC), watchdog timer, and real-time clock (RTC).
- System counter
- Triple-timer counter
- System watchdog timer
- Real-time clock
Software Build Flow
Objective: Provide an overview of the different build flows, such as the do it yourself, Yocto Project, and PetaLinux tool flows.
- Embedded Linux system
- Build systems to build an embedded Linux environment
Software Stack
Objective: Review the Versal ACAP bare-metal, FreeRTOS, and Linux software stack and their components.
- The bare-metal and FreeRTOS software stack in the Versal® ACAP
- Linux software stack in the Versal ACAP
- Components of the Linux software stack
DSP Engine
Objective: Describe the DSP58 slice and compares the DSP58 slice with the DSP48 slice. DSP58 modes are also covered in detail.
- DSP58 architecture and its features in the Versal® ACAP
- Differences between the DSP58 and DSP48E2 slices
- Modes of operation supported by the DSP58 slice
AI Engine
Objective: Discuss the AI Engine array architecture, terminology, and AIE interfaces.
- Architecture of the Versal® AI Engine
- Multiple levels of parallelism
- Scalar unit and floating-point unit of the AI Engine
- AI Engine module interfaces
NoC Introduction and Concepts
Objective: Cover the reasons to use the network on chip, its basic elements, and common terminology.
- The Versal® network on chip (NoC)
- NoC terminology
- Concept of the NoC and its features
Device Memory
Objective: Describe the available memory resources, such as block RAM, UltraRAM, LUTRAM, embedded memory, OCM, and DDR. The
integrated memory controllers are also covered.
- Configurable PL-building block memories in the Versal® architecture
- On-chip memory hierarchy
- External memory and integrated memory controllers
Programming Interfaces
Objective: Review the various programming interfaces in the Versal ACAP.
- Programming interfaces available in the Versal® ACAP
- Address maps for these programming interfaces
Application Partitioning
Objective: Cover what application partitioning is and how the mapping of resources based on the models of computation can be performed.
- Application partitioning to accelerate
- Application partitioning on the different compute engines in Versal® ACAPs
PCI Express & CCIX
Objective: Provide an overview of the CCIX PCIe module and describes the PL and CPM PCIe blocks.
- PCI Express solutions in the Versal® ACAP
- Integrated Block for PCI Express
- CPM module for PCI Express
- PHY for PCI Express
- Xilinx DMA solutions for PCI Express in the Versal ACAP
- Right PCIe option for your design
- Benefits of CCIX technology
Serial Transceivers
Objective: Describe the transceivers in the Versal ACAP.
- Serial transceiver solutions in the Versal® ACAP
- Main features of the Versal ACAP serial transceivers
- Transceiver tile
- GT transmitter and receiver architecture and functionality
Power and Thermal Solutions
Objective: Discuss the power domains in the Versal ACAP as well as power optimization and analysis techniques. Thermal design challenges are also covered.
- Versal® ACAP power solution
- Power domains in the Versal ACAP
- Power management modes in the Versal ACAP
- Thermal challenges in the Versal ACAP
Debugging
Objective: Cover the Versal ACAP debug interfaces, such as the test access port (TAP), debug access port (DAP) controller, and
high-speed debug port (HSDP).
- Debug interfaces in the Versal® ACAP
- Test access port (TAP) and debug access port (DAP) controller
- High-speed debug port (HSDP)
- SmartLynq+ module for debugging
Security Features
Objective: Describe the security features of the Versal ACAP.
- Importance of security in semiconductor devices
- Common types of security attacks
- Various security features found in Versal® ACAP devices
- Enhanced security features available in Versal ACAPs compared to other Xilinx devices
System Simulation
Objective: Explain how to perform system-level simulation in a Versal ACAP design.
- Importance of system-level simulation
- System simulation methodology for Versal® ACAPs as well as the different flows
- Simulation scope for hardware and software development
- QEMU-RTL co-simulation
Board System Design Methodology
Objective: Describe PCB, power, clocking, and I/O considerations when designing a system.
- PCB design considerations for the Versal® ACAP
- Power aspects for the Versal ACAP
- Clock resource and I/O planning guidelines
System and Solution Planning Methodology
Objective: Describe design partitioning, power, and thermal guidelines. Also reviews system debug, verification, and validation planning.
- System design methodology flow for the Versal® ACAP
- design partitioning considerations
- Power and thermal considerations
- System debug, verification, and validation planning
Hardware, IP, and Platform Development Methodology
Objective: Describe the different Versal ACAP design flows and covers the platform creation process using the Vivado IP integrator, RTL, HLS, and Vitis environment.
- The different Versal® ACAP design flows
- Platform creation process
System Integration and Validation Methodology
Objective: Describe different simulation flows as well as timing and power closure techniques. Also explains how to improve system performance.
- The different simulation flows for the Versal® ACAP
- Timing and power closure techniques
- Improve Versal ACAP system performance