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Designing with the Versal Adaptive Soc: PCI Express Systems
Versal
Designing with the Versal ACAP: PCI Express Systems
Introduces the features and capabilities of the PCIe® and
Cache Coherent Interconnect blocks in the Versal™ architecture.
Course
Highlights
This two-day course introduces the features and capabilities of the PCIe® and Cache Coherent Interconnect blocks in the Versal™ architecture. Learn how to implement a Versal ACAP PCI Express® solution in custom applications to improve time to market.
The emphasis of this course is on:
- Describing the Xilinx PCI Express design methodology
- Enumerating various Xilinx PCI Express core products
- Selecting the PCI Express IP cores from the Vivado® Design Suite
- Generating PCI Express example designs and simple applications
- Identifying the advanced capabilities of the PCIe specification
This course also focuses on the AXI-Streaming interconnect.
Who Should
Attend
- Hardware designers who want to create applications using Xilinx IP cores for PCI Express
- Software engineers who want to understand the deeper workings of the Xilinx PCI Express solution
- System architects who want to leverage key Xilinx advantages related to performance, latency, and bandwidth in PCI Express
applications
Course
Prerequisites
- Experience with the PCI/PCIe specification protocol
- Knowledge of VHDL or Verilog
- Some experience with Xilinx implementation tools
- Some experience with a simulation tool, preferably the Vivado® simulator
- Moderate digital design experience
Course
Benefits
After completing this comprehensive training, you will have the necessary skills to construct a basic PCI Express system by:
- Selecting the appropriate IP for your application
- Specifying requirements of an endpoint application
- Connecting PCIe IPs with the user application
- Utilizing PL and PS resources supporting PCI Express
- Simulating and implementing PCI Express systems
- Identify the advanced capabilities of the PCI Express specification
protocol and feature set
Partners
Upcoming Program
- Please keep me posted on the next schedule
- Please contact me to arrange customized/ in-house training
Course Outline
Introduction to PCI Express
Objective: Introduces the course and discusses a few key topics of the PCI Express protocol.
- Describe the basics, advantages, and limitations of the PCI™ technology
- Describe the basic PCI Express® architecture
Versal ACAP PCIe Solutions Overview
Objective: Provides an overview of the Xilinx PCI Express solutions in the Versal architecture and identifies key differentiators.
- List the PCI Express solutions in the Versal™ ACAP
PCIe Block Architecture and Functionality
Objective: Describes the PL PCIe block architecture. You will learn details on the block features and functionality.
- Describe the architecture of the PCIe block
- Identify the features of the PCIe block
Versal ACAP: PCIe Block Interfaces Overview
Objective: Provides an overview of the PL PCIe block interfaces. Deeper discussion on physical layer and general interfaces.
- Describe the PCIe® block interfaces
- Describe the default and optional control options
Versal ACAP: PCIe Block Requester Interfaces
Objective: Reviews the requester AXI4-Streaming core interfaces. You will learn how to utilize packet descriptors for request interfaces.
- Describe the requester interfaces for the PCIe block core
- Utilize packet descriptors for requests
Versal ACAP: PCIe Block Completer Interfaces
Objective: Reviews the completer AXI4-Streaming core interfaces. You will learn how to utilize packet descriptors for completion interfaces.
- Describe the completer interfaces for the PCIe block core
- Utilize packet descriptors for completions
Versal ACAP: PCIe Block Customization
Objective: Illustrates customizing the PL PCIe block. You will learn how to utilize the various configuration options.
- Customize a PL PCIe block
- Describe the configuration options
Versal ACAP: PCIe Block Test Bench and Simulation
Objective: Discusses PCIe block simulation. You will learn how to utilize the generated example design to verify the functionality of the PL PCIe solution.
- Identify the different types of simulation methods for PCIe designs and when to run each type of simulation
- Prepare an appropriate test bench
Versal ACAP: PCIe Block Implementation
Objective: Discusses implementation topics. You will review the placement recommendations for the PL PCIe blocks, transceivers, clocks, and resets.
- Describe the placement rules for the PCIe blocks and serial transceivers
- Describe the PCIe block clock and reset pin location requirements
Versal ACAP: PL PCIe Block Debugging Overview
Objective: Describes the PCI Express debugging options in the Versal ACAP PCI Express physical and transaction layers. You will learn how to perform PCI Express link debug.
- Describe debugging and verification methodologies for the Versal™ ACAP PL PCIe block
- Identify tools that can help with PCIe debugging
Introduction to DMA
Objective: Reviews DMA basics and describes DMA in the context of the PCI Express standard.
- Describe the significance of the DMA in the context of the PCIe® standard
PL PCIe XDMA/Bridge Subsystem
Objective: Describes the Xilinx XDMA architecture and features as well as DMA descriptor usage and interface options. You will learn how to utilize the Xilinx XDMA subsystem.
- Describe the features of Xilinx DMA
- Describe the Xilinx DMA descriptors
- Identify the supported interface options
PL PCIe QDMA Subsystem
Objective: Describes the Xilinx QDMA architecture and features. You will learn how to utilize the Xilinx QDMA subsystem and its queue usage.
- Describe the features of QDMA
- Describe the QDMA blocks
- Describe queue usage
Versal ACAP: CPM4 Architecture and Functionality
Objective: Describes the CPM4 block architecture and functionality. You will learn the commonalities and differences to the PL PCIe solution.
- Describe the CPM4 architecture
- List the CPM4 features
Versal ACAP: CPM Block Customization
Objective: Reviews the configuration options of the CIPS CPM block. You will learn how to customize the CPM PCIe block.
- Customize the CIPS CPM block
- Describe the configuration options
Versal ACAP: CPM IP Use Cases
Objective: Describes typical use cases for the Versal ACAP PCI Express solutions to enable you to select the right solution for your design requirements.
- Describe typical use cases for the Versal™ ACAP PCI Express® solutions
- Select the right use case to fit your design requirements