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High-Level Synthesis with the Vitis Unified IDE
Vitis Unified Software/Language/High Level Synthesis
High-Level Synthesis with the Vitis Unified IDE
Enhance productivity using the Vitis Unified IDE
Course
Highlights
This course provides a thorough introduction to the Vitis™ High-Level Synthesis (HLS) using the AMD Vitis™ Unified IDE.
The focus of this course is on:
- Converting C/C++ designs into RTL implementations
- Learning HLS component development flow
- Creating I/O interfaces for designs
- Applying different optimization techniques to design
- improving throughput, area, latency, and logic by using different HLS pragmas/directives
- Exporting IP that can be used with the Vivado® IP catalog
- Migrating designs from the classic Vitis HLS tool to the Vitis Unified IDE
What’s New for 2023.2
- Restructured existing Vitis HLS content to align with the HLS component development flow
- Revamped all labs for compatibility with the Vitis Unified IDE
- Integrated coverage of the v++ and vitis-run command options
- Added information on Vitis HLS Code Analyzer and the Dataflow Viewer
- Added a module dedicated to optimizing AXI system performance
- Added a module covering Vitis HLS Libraries
- Added a module and lab for migrating from the classic Vitis HLS tool to the Vitis Unified IDE
Who Should
Attend
Software and hardware engineers looking to utilize high-level synthesis
Course
Prerequisites
- C or C++ knowledge
- Basic RTL design flow knowledge
Course
Benefits
After completing this comprehensive training, you will have the
necessary skills to:
- Enhance productivity by using the AMD Vitis Unified IDE for HLS component development
- Describe the HLS component development flow
- Use the Vitis Unified IDE to create an HLS component
- Identify common coding pitfalls as well as methods for improving RTL/hardware code
- Use directives/pragmas to improve throughput, area, latency, and logic and to select RTL interfaces
- Perform system-level integration of IP generated by the Vitis Unified IDE
- Migrate designs from the classic Vitis HLS tool to the Vitis Unified IDE
Partners
Upcoming Program
- Please keep me posted on the next schedule
- Please contact me to arrange customized/ in-house training
Course Outline
Introduction to High-Level Synthesis
Objective: Provides an overview of high-level synthesis (HLS), the Vitis Unified IDE for HLS flow, and the verification advantage.
HLS Component Development Flow
Objective: Explores the HLS component development flow in the Vitis Unified IDE.
Abstract Parallel Programming Model for HLS
Objective: Describes the structuring of a design at a high level using an abstract parallel programming model.
Design Exploration with Directive
Objective: Explores different optimization techniques that can improve design performance.
HLS Component Development Using the Command Line
Objective: Describes the unified command line interface and the the v++ and vitis-run commands.
Introduction to Vitis HLS Design Methodology
Objective: Introduce the methodology guidelines covered in this course and the HLS Design Methodology steps.
Introduction to I/O Interfaces
Objective: Explain interfaces such as the block-level and port-level protocols abstracted by the Vitis HLS from a C design.
Block-Level Protocols
Objective: Explain the different types of block-level protocols abstracted by the Vitis HLS.
Port-Level I/O Protocols
Objective: Describe the port-level interface protocols abstracted by the Vitis HLS from the C design.
AXI Adapter Interface Protocols
Objective: Explain the different AXI interfaces (such as AXI4-Master, AXI4-Lite (Slave), and AXI4-Stream) supported by the Vitis HLS.
Pipeline for Performance: PIPELINE
Objective: Describe the PIPELINE directive for improving the throughput of a design.
Optimizing for Performance: DATAFLOW
Objective: Describe the DATAFLOW directive for improving the throughput of a design by pipelining the functions to execute as soon as possible.
Optimizing for Throughput
Objective: Describles the performance limitations caused by arrays in your design. Also explore optimization techniques to handle arrays for improving performance.
Optimizing for Latency: Default Behavior
Objective: Describe the default behavior of the Vitis HLS on latency and throughput.
Optimizing for Latency: Reducing Latency
Objective: Describes how to optimize the C design to improve latency.
Optimizing for Area and Logic
Objective: Describe different methods for improving resource utilization and explains how some of the directives have impact on the area utilization.
Optimizing AXI System Performance
Objective: Describes AXI burst transfers and their types. Also outlines the optimization steps to improve system performance.
Vitis HLS Libraries
Objective: Describes the library support offered by Vitis HLS.
Vitis HLS Libraries: Arbitrary Precision Data Types
Objective: Describe Vitis HLS tool support for the C/C++ languages as well as arbitrary precision data types.
Using Pointers in the Vitis HLS
Objective: Explain the use of pointers in the design and workarounds for some of the limitations.
HLS Component Design Flow – System Integration
Objective: Illustrates the process of developing and exporting an HLS component as Vivado IP.
Migrating to the Vitis Unified IDE - HLS Component
Objective: Describes the need for the Vitis Unified IDE and identifies different approaches for migrating projects from the classic Vitis HLS tool to the Vitis Unified IDE.
